Related to: #35597

The proposal is basically to expose load barrier functionality to the user in a form of public API.

On systems with strong memory models the API will only impact program/compiler reordering. On weak memory models an appropriate memory barrier instruction will be emitted.

In addition to ReadMemoryBarrier a symmetrical WriteMemoryBarrier should be considered.

One thing that could be a subject of discussions is the specified strength of the barriers.-

• whether the ReadMemoryBarrier is Load-Load or Load-Load/Store
• whether the WriteMemoryBarrier is Store-Store or Load/Store-Store

The tradeoff here is that weaker guarantee would reduce applicability of the the APIs, while stronger guarantee could force some implementations to implement the barrier as a full barrier.

For reference:

• x86/x64 either kind of a barrier is a noop, only compiler order needs to be preserved.
• arm32 either kind of a barrier would need to be emitted as a full barrier
• arm64 has instructions for Load-Load/Store and Store-Store barriers. (not symmetrical!)
• MIPS has instructions for Load-Load/Store and Load/Store-Store barriers.