The 128-bit of interface dispatch cache entry and indirection cell's stub/cache mismatch the PalInterlockedCompareExchange128's atomically requirements #109276
Description
Description
I have some question about the CAS-128bit when updating and loading the 128-bit data.
runtime/src/coreclr/nativeaot/Runtime/amd64/StubDispatch.S
Lines 30 to 32 in 5d09a8f
Are these codes related with the CAS-128-bit data?
If yes, is there some problem if the 128-bit data are loaded by two instructions rather than a 128-bit load instruction? When finished the first 64-bit pointer loading, the CAS-128-bit update the whole 128-bit date, then the second loading will get a new value but now the old value.
Reproduction Steps
When finished the first 64-bit pointer loading, the CAS-128-bit update the whole 128-bit date, then the second loading will get a new value but now the old value.
Expected behavior
should load the 128-bit date by one instruction atomically.
Actual behavior
But now these code will hit the wrong value at the very low possibility.
Regression?
No response
Known Workarounds
No response
Configuration
No response
Other information
No response