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AndyAyersMSCopilot
AndyAyersMS
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Copilot
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[Wasm RyuJit] Add Wasm SIMD NYIs, fix PushArgs assert, fix Async/Try/SCC issue. (#129494)
- Report SIMD16 local loads as Wasm SIMD NYIs so R2R compilation can skip them when configured. - Avoid assuming retbuf call arguments are PUTARG nodes on targets without a fixed register set (Wasm). - Add temporary bidirectional edges for isolated async try side entries so SCC rewriting can see them. This handles cases where the in-try resumption target is not reachable from the try entry and throws. --------- Co-authored-by: Copilot <[email protected]>
1 parent bf44774 commit a17debe

4 files changed

Lines changed: 50 additions & 5 deletions

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‎src/coreclr/jit/codegencommon.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1789,9 +1789,12 @@ void CodeGen::genEmitCallWithCurrentGC(EmitCallParams& params)
17891789
if (retBuf != nullptr)
17901790
{
17911791
GenTree* node = retBuf->GetNode();
1792-
assert(node->OperIsPutArg());
17931792

1793+
#if HAS_FIXED_REGISTER_SET
1794+
assert(node->OperIsPutArg());
17941795
node = node->gtGetOp1()->gtSkipReloadOrCopy();
1796+
#endif
1797+
17951798
if (!node->OperIs(GT_LCL_ADDR))
17961799
{
17971800
return;

‎src/coreclr/jit/codegenwasm.cpp‎

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2441,9 +2441,15 @@ void CodeGen::genCodeForLclFld(GenTreeLclFld* tree)
24412441
{
24422442
assert(tree->OperIs(GT_LCL_FLD));
24432443
LclVarDsc* varDsc = m_compiler->lvaGetDesc(tree);
2444+
var_types type = tree->TypeGet();
2445+
2446+
if (type == TYP_SIMD16)
2447+
{
2448+
NYI_WASM_SIMD("SIMD16 local field load");
2449+
}
24442450

24452451
GetEmitter()->emitIns_I(INS_local_get, EA_PTRSIZE, GetFramePointerRegIndex());
2446-
GetEmitter()->emitIns_S(ins_Load(tree->TypeGet()), emitTypeSize(tree), tree->GetLclNum(), tree->GetLclOffs());
2452+
GetEmitter()->emitIns_S(ins_Load(type), emitTypeSize(tree), tree->GetLclNum(), tree->GetLclOffs());
24472453
WasmProduceReg(tree);
24482454
}
24492455

@@ -2465,6 +2471,11 @@ void CodeGen::genCodeForLclVar(GenTreeLclVar* tree)
24652471
if (!varDsc->lvIsRegCandidate())
24662472
{
24672473
var_types type = varDsc->GetRegisterType(tree);
2474+
if (type == TYP_SIMD16)
2475+
{
2476+
NYI_WASM_SIMD("SIMD16 local load");
2477+
}
2478+
24682479
GetEmitter()->emitIns_I(INS_local_get, EA_PTRSIZE, GetFramePointerRegIndex());
24692480
GetEmitter()->emitIns_S(ins_Load(type), emitTypeSize(type), tree->GetLclNum(), 0);
24702481
WasmProduceReg(tree);
@@ -2549,8 +2560,13 @@ void CodeGen::genCodeForIndir(GenTreeIndir* tree)
25492560
{
25502561
assert(tree->OperIs(GT_IND));
25512562

2552-
var_types type = tree->TypeGet();
2553-
instruction ins = ins_Load(type);
2563+
var_types type = tree->TypeGet();
2564+
if (type == TYP_SIMD16)
2565+
{
2566+
NYI_WASM_SIMD("SIMD16 indirect load");
2567+
}
2568+
2569+
instruction ins = ins_Load(type);
25542570

25552571
genConsumeAddress(tree->Addr());
25562572

@@ -3571,6 +3587,11 @@ void CodeGen::genLoadLocalIntoReg(regNumber targetReg, unsigned lclNum)
35713587
{
35723588
LclVarDsc* varDsc = m_compiler->lvaGetDesc(lclNum);
35733589
var_types type = varDsc->GetRegisterType();
3590+
if (type == TYP_SIMD16)
3591+
{
3592+
NYI_WASM_SIMD("SIMD16 local load");
3593+
}
3594+
35743595
GetEmitter()->emitIns_I(INS_local_get, EA_PTRSIZE, GetFramePointerRegIndex());
35753596
GetEmitter()->emitIns_S(ins_Load(type), emitTypeSize(type), lclNum, 0);
35763597
GetEmitter()->emitIns_I(INS_local_set, emitTypeSize(type), WasmRegToIndex(targetReg));

‎src/coreclr/jit/flowgraph.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7982,6 +7982,27 @@ void FlowGraphTryRegions::AddMultipleEntryRegionEdges(ArrayStack<FlowEdge*>& edg
79827982
// And an edge from method entry to dest.
79837983
FlowEdge* const entryDestEdge = m_compiler->fgAddRefPred(destBlock, m_compiler->fgFirstBB);
79847984
edges.Push(entryDestEdge);
7985+
7986+
// If the dest is not reachable within the try, then we need to also add
7987+
// a temporary edge from the try header to the dest to create the SCC.
7988+
// Since we've pruned away dead blocks, any other pred edge suffices to
7989+
// establish reachability.
7990+
//
7991+
bool isReachableInTry = false;
7992+
for (FlowEdge* const predEdge : destBlock->PredEdges())
7993+
{
7994+
if (predEdge != edge)
7995+
{
7996+
isReachableInTry = true;
7997+
break;
7998+
}
7999+
}
8000+
8001+
if (!isReachableInTry)
8002+
{
8003+
FlowEdge* const headerDestEdge = m_compiler->fgAddRefPred(destBlock, headerBlock);
8004+
edges.Push(headerDestEdge);
8005+
}
79858006
}
79868007
}
79878008
}

‎src/coreclr/jit/layout.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ class ClassLayout
202202
case 8:
203203
return TYP_LONG;
204204
#endif
205-
#ifdef FEATURE_SIMD
205+
#if defined(FEATURE_SIMD) && !defined(TARGET_WASM)
206206
// TODO: check TYP_SIMD12 profitability,
207207
// it will need additional support in `BuildStoreLoc`.
208208
case 16:

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