-
Notifications
You must be signed in to change notification settings - Fork 1.7k
Update Interlocked.xml #4962
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Update Interlocked.xml #4962
Conversation
The documentation re. `Interlocked.Read` for 64-bit reads sized reads on 64-bit systems is simply not correct. There is known architecture in existence where a 64-bit value that spans across two cache lines can be read without the use of atomic operations. For example, consult [Intel's Software Development Manual, Volume 3A](https://software.intel.com/content/dam/develop/public/us/en/documents/253668-sdm-vol-3a.pdf) which clearly states on section 8.1.1: > Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel® Atom™, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided Atomic operations are required for such cases, and those cases (split cache-line access) while uncommon in .NET are not impossible.
|
Docs Build status updates of commit 6211bfb: ✅ Validation status: passed
For more details, please refer to the build report. Note: Broken links written as relative paths are included in the above build report. For broken links written as absolute paths or external URLs, see the broken link report. For any questions, please:
|
E.g. with such a struct? [StructLayout(LayoutKind.Explicit)]
public struct Bar
{
[FieldOffset(0)]
public byte A;
[FieldOffset(1)]
public long B;
[FieldOffset(9)]
public byte C;
[FieldOffset(10)]
public long D;
}
|
Co-authored-by: Shay Rojansky <[email protected]>
Yeap. This used to be the more common way of getting to this sort of situation, but with the advent of .NET Span you have new ways of getting to this sort of situation. |
|
Docs Build status updates of commit 979e162: ✅ Validation status: passed
For more details, please refer to the build report. Note: Broken links written as relative paths are included in the above build report. For broken links written as absolute paths or external URLs, see the broken link report. For any questions, please:
|
|
I believe interlocked operations on 64-bit memory locations have a requirement for the memory location to be aligned to 8 bytes, so they cannot cross a cache line boundary. I don't think there is a way to do atomic operations on unaligned 64-bit memory locations. |
None of the above is true for Intel / x86 architectures:
Reference Intel docs / text explaining (1)-(3) was linked in the original comment at the top of this issue. |
|
True, but that doesn't seem to be the case for ARM architectures, where load/store-exclusive instructions seem to require alignment in many if not all cases, with perhaps a stricter requirement on the size of the locked region (within which unaligned accesses may be allowed) than the size of a cache line. The interlocked read prevents tearing on 32-bit systems (similarly to
Maybe some more guidance would be useful, suggestions? |
|
That's something different then... 👍 All I'm saying is that this PR, specifically, corrects a false statement:
Into a correct one:
I think that the issue of alignment is more of a conceptual issue that is probably best addressed in general in some conceptual-level documentation of the Maybe something such as a "See Also" link from this page pointing to a dedicated page that discusses alignment, can even (gasp!) link to the actual relevant documentation per supported architecture in .NET (e.g. x86 + arm) and give the proper context... Makes sense? |
|
Yea maybe the general guidance should be in the |
|
Hi @damageboy; I think there's a piece of feedback left to address here. Would you like to update the PR for approval? Thanks! |
The documentation re.
Interlocked.Readfor 64-bit reads sized reads on 64-bit systems is simply not correct.There is no known architecture in existence where a 64-bit value that spans across two cache lines can be read without the use of atomic operations.
For example, consult Intel's Software Development Manual, Volume 3A which clearly states on section 8.1.1:
Atomic operations are required for such cases, and those cases (split cache-line access) while uncommon in .NET are not impossible.
Summary
Describe your changes here.
Fixes #Issue_Number (if available)