Implement SSE4.1 Insert/Extract and simplify SSE/SSE2 intrinsic by fiigii · Pull Request #16646 · dotnet/coreclr

fiigii · 2018-02-28T01:45:20Z

This PR

updates the table-driven framework to unify throwing PNSE from r64 instructions on 32-bit platforms and simplify SSE/SSE2 intrinsic code(close https://github.com/dotnet/coreclr/issues/16342).
implements SSE4.1 Insert and Extract and marks SSE4.1 as complete.

fiigii · 2018-02-28T01:48:55Z

src/jit/namedintrinsiclist.h

-    // Select base type using argument type
-    HW_Flag_BaseTypeFromArg = 0x400,
+    // Select base type using the first argument type
+    HW_Flag_BaseTypeFromFirstArg = 0x400,


With this change, all the intrinsics (except MemoryStore) that return a scalar value (e.g., bool) should explicitly have flag HW_Flag_BaseTypeFromFirstArg or HW_Flag_BaseTypeFromSecondArg. cc @4creators

Speaking of asserts (which we were a few hours ago on another thread), this seems like something that could be asserted somewhere - e.g. a pass over the table that validates these kinds of properties. There are probably other consistency checks across signature, category and flag that could be checked.

@fiigii, could you log an issue tracking this?

tannergooding · 2018-02-28T03:00:40Z

src/jit/compiler.h

    GenTree* impNonConstFallback(NamedIntrinsic intrinsic, var_types simdType, var_types baseType);
    static bool isImmHWIntrinsic(NamedIntrinsic intrinsic, GenTree* lastOp);
    GenTree* addRangeCheckIfNeeded(NamedIntrinsic intrinsic, GenTree* lastOp, bool mustExpand);
+    bool signatureTypeSupproted(var_types retType, CORINFO_SIG_INFO* sig, HWIntrinsicFlag flags);


nit: Supproted->Supported

tannergooding · 2018-02-28T03:04:34Z

src/jit/hwintrinsicxarch.cpp

+//
+// Return Value:
+//    On 32-bit platforms, return true if the intrinsic does not use any 64-bit registers (r64)
+bool Compiler::signatureTypeSupproted(var_types retType, CORINFO_SIG_INFO* sig, HWIntrinsicFlag flags)


These needs to have HWIntrinsic in the name somewhere.

tannergooding · 2018-02-28T03:07:26Z

src/jit/namedintrinsiclist.h

+    // 64-bit intrinsics
+    // Intrinsics that operate over 64-bit general purpose registers are not supported on 32-bit platform
+    HW_Flag_64BitOnly           = 0x4000,
+    HW_Flag_firstArgMaybe64Bit  = 0x8000,


nit: Fix casing on First

tannergooding · 2018-02-28T03:10:11Z

src/jit/hwintrinsiclistxarch.h

+HARDWARE_INTRINSIC(SSE_ConvertToInt32,                               "ConvertToInt32",                                   SSE,        -1,           16,           1,           {INS_invalid,   INS_invalid,     INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtss2si,  INS_invalid},           HW_Category_SIMDScalar,                        HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SSE_ConvertToInt64,                               "ConvertToInt64",                                   SSE,        -1,           16,           1,           {INS_invalid,   INS_invalid,     INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtss2si,  INS_invalid},           HW_Category_SIMDScalar,                        HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SSE_ConvertToSingle,                              "ConvertToSingle",                                  SSE,        -1,           16,           1,           {INS_invalid,   INS_invalid,     INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_movss,     INS_invalid},           HW_Category_Helper,                            HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SSE_ConvertScalarToVector128Single,               "ConvertScalarToVector128Single",                   SSE,        -1,           16,           2,           {INS_invalid,   INS_invalid,     INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtsi2ss,  INS_invalid},           HW_Category_SIMDScalar,                        HW_Flag_SecondArgMaybe64Bit|HW_Flag_BaseTypeFromFirstArg)


This needs to be marked as CopyUpperBits

tannergooding · 2018-02-28T03:13:58Z

src/jit/hwintrinsiclistxarch.h

-HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128Double,              "ConvertScalarToVector128Double",                   SSE2,       -1,           16,          2,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtsi2sd,  INS_invalid,   INS_cvtsi2sd,  INS_invalid,   INS_cvtss2sd,  INS_invalid},           HW_Category_Special,                           HW_Flag_NoFlag)
-HARDWARE_INTRINSIC(SSE2_ConvertToVector128Int32,                     "ConvertToVector128Int32",                          SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtps2dq,  INS_cvtpd2dq},          HW_Category_SimpleSIMD,                        HW_Flag_BaseTypeFromArg)
+HARDWARE_INTRINSIC(SSE2_ConvertToDouble,                             "ConvertToDouble",                                  SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_movsd},             HW_Category_Helper,                            HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SSE2_ConvertToInt32,                              "ConvertToInt32",                                   SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_mov_xmm2i, INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtsd2si},          HW_Category_SIMDScalar,                        HW_Flag_BaseTypeFromFirstArg|HW_Flag_MultiIns)


Why is this one (and the following) MultiIns?

Because these intrinsics need special CodeGen (but can be table-driven in the importer). Probably, I should add a new flag?

Probably, I should add a new flag

I think so. I don't believe we want to use MultiIns for anything other than intrinsics which generate multiple instructions

tannergooding · 2018-02-28T03:15:08Z

src/jit/hwintrinsiclistxarch.h

+HARDWARE_INTRINSIC(SSE2_ConvertToUInt32,                             "ConvertToUInt32",                                  SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_mov_xmm2i, INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid},           HW_Category_SIMDScalar,                        HW_Flag_BaseTypeFromFirstArg|HW_Flag_MultiIns)
+HARDWARE_INTRINSIC(SSE2_ConvertToUInt64,                             "ConvertToUInt64",                                  SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_mov_xmm2i, INS_invalid,   INS_invalid},           HW_Category_SIMDScalar,                        HW_Flag_BaseTypeFromFirstArg|HW_Flag_MultiIns)
+HARDWARE_INTRINSIC(SSE2_ConvertToVector128Double,                    "ConvertToVector128Double",                         SSE2,       -1,           16,          1,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtdq2pd,  INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtps2pd,  INS_invalid},           HW_Category_SimpleSIMD,                        HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128Double,              "ConvertScalarToVector128Double",                   SSE2,       -1,           16,          2,            {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_cvtsi2sd,  INS_invalid,   INS_cvtsi2sd,  INS_invalid,   INS_cvtss2sd,  INS_invalid},           HW_Category_Special,                           HW_Flag_SecondArgMaybe64Bit|HW_Flag_MultiIns)


You changed the corresponding SSE one off of Special, why not this one?

Good catch! Will fix.

fiigii · 2018-02-28T22:09:04Z

Implemented SSE4.1 Insert and Extract. Since these two intrinsics rely on the above work (64-bit intrinsics), so push the implementation in this PR to avoid blocking.

@CarolEidt @tannergooding PTAL

fiigii · 2018-02-28T22:11:29Z

tests/src/JIT/HardwareIntrinsics/X86/Shared/GenerateTests.csx

+    ("InsertScalarTest.template",new string[] { "Sse2", "Sse2",    "Insert",                               "Vector128",  "Int16",     "Vector128",   "Int16",          "1",  "(short)2", "16", "(short)0",                                               "(i == 1 ? result[i] != 2 : result[i] != 0)"}),
+    ("InsertScalarTest.template",new string[] { "Sse2", "Sse2",    "Insert",                               "Vector128",  "UInt16",    "Vector128",   "UInt16",         "1",  "(ushort)2","16", "(ushort)0",                                              "(i == 1 ? result[i] != 2 : result[i] != 0)"}),
+    ("InsertScalarTest.template",new string[] { "Sse2", "Sse2",    "Insert",                               "Vector128",  "Int16",     "Vector128",   "Int16",          "129","(short)2", "16", "(short)0",                                               "(i == 1 ? result[i] != 2 : result[i] != 0)"}),
+    ("InsertScalarTest.template",new string[] { "Sse2", "Sse2",    "Insert",                               "Vector128",  "UInt16",    "Vector128",   "UInt16",         "129","(ushort)2","16", "(ushort)0",                                              "(i == 1 ? result[i] != 2 : result[i] != 0)"}),


Made two new templates for insert and extract.
@4creators I implemented SSE2 insert and extract in this PR as well, if you have done on them, I can remove here.

@fiigii I have implemented them as well

@4creators Sounds Good, could you submit your current work or open an issue to keep sync with us?

fiigii · 2018-02-28T22:14:10Z

src/jit/hwintrinsiclistxarch.h

+HARDWARE_INTRINSIC(SSE41_Extract,                                    "Extract",                                          SSE41,      -1,           16,           2,           {INS_pextrb,    INS_pextrb,    INS_invalid,   INS_invalid,    INS_pextrd,    INS_pextrd,    INS_pextrq,    INS_pextrq,    INS_extractps, INS_invalid},          HW_Category_IMM,                               HW_Flag_FullRangeIMM|HW_Flag_BaseTypeFromFirstArg|HW_Flag_MultiIns|HW_Flag_NoRMWSemantics)
 HARDWARE_INTRINSIC(SSE41_Floor,                                      "Floor",                                            SSE41,       9,           16,           1,           {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,    INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_roundps,   INS_roundpd},          HW_Category_SimpleSIMD,                        HW_Flag_NoRMWSemantics)
 HARDWARE_INTRINSIC(SSE41_FloorScalar,                                "FloorScalar",                                      SSE41,       9,           16,          -1,           {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,    INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_roundss,   INS_roundsd},          HW_Category_Special,                           HW_Flag_CopyUpperBits)
+HARDWARE_INTRINSIC(SSE41_Insert,                                     "Insert",                                           SSE41,      -1,           16,           3,           {INS_pinsrb,    INS_pinsrb,    INS_invalid,   INS_invalid,    INS_pinsrd,    INS_pinsrd,    INS_pinsrq,    INS_pinsrq,    INS_insertps,  INS_invalid},          HW_Category_IMM,                               HW_Flag_FullRangeIMM|HW_Flag_SecondArgMaybe64Bit)


@tannergooding Shall I give Insert a HW_Flag_NoRMWSemantics as well?

It should only be on instructions that don't need hasDelayFreeSrc on op2.

I think pinsrb/pinsrd/pinsrq qualify here (since op2 is an integer reg and taget is an xmm reg).

However, insertps shouldn't have it, since op2 is also an xmm reg and we need to ensure that op2 is different from targetReg

Okay, looks like Insert should not have it.

You'll need to ensure that pinsrb/d/q are specially handled

fiigii · 2018-03-01T06:33:00Z

@CarolEidt could you please take a look at this PR?

CarolEidt · 2018-03-01T06:38:15Z

@fiigii I am just getting on a plane. I should be able to review it in a few hours. Sorry for the delay.

fiigii · 2018-03-01T06:40:18Z

@CarolEidt No worries, thank you 😄

tannergooding · 2018-03-01T06:46:30Z

src/jit/emitxarch.cpp

+#ifndef LEGACY_BACKEND
+                if (ins == INS_extractps)
+                {
+                    mReg = id->idReg1();


Why can't we handle this in codegen?

Hmm..we can. The special case extractps uses ModRM:r/m for the dst register (store semantics).
I will handle this in codgen, thanks!

tannergooding · 2018-03-01T06:54:19Z

src/jit/lsraxarch.cpp

+        case NI_SSE41_Extract:
+            if (intrinsicTree->gtSIMDBaseType == TYP_FLOAT)
+            {
+                info->internalIntCount += 1;


This is needed to get the value back in an XMM register, correct?

Yes, the original extractps instruction writes the result (a floating-point number) into a GPR, but our API returns a float. So we need the int-register as the dst of extractps.

tannergooding · 2018-03-01T06:54:57Z

src/jit/instrsxarch.h

+INST3( pextrb,       "pextrb"      , 0, IUM_WR, 0, 0, SSE3A(0x14),  BAD_CODE, BAD_CODE)      // Extract Byte
+INST3( pextrd,       "pextrd"      , 0, IUM_WR, 0, 0, SSE3A(0x16),  BAD_CODE, BAD_CODE)      // Extract Dword
+INST3( pextrq,       "pextrq"      , 0, IUM_WR, 0, 0, SSE3A(0x16),  BAD_CODE, BAD_CODE)      // Extract Qword
+INST3( extractps,    "extractps"   , 0, IUM_WR, 0, 0, BAD_CODE,     BAD_CODE, SSE3A(0x17))   // Extract float


nit: I believe most of these names have been copied out of the Arch manual... So this should probably be Extract Packed Floating-Point Values

Good catch, thanks!

tannergooding · 2018-03-01T06:56:36Z

src/jit/hwintrinsicxarch.cpp

    if (impIsTableDrivenHWIntrinsic(category, flags))
    {
-        if (!varTypeIsSIMD(retType) || ((flags & HW_Flag_BaseTypeFromArg) != 0))
+        if (category == HW_Category_MemoryStore ||


NOTE: I had to move this block in my AVX PR (#16655) in order to deal with the intrinsics that have both generic and non-generic overloads.

CarolEidt

Looks good overall, but needs minor changes: comments & parentheses.
I mention a suggestion for a consistency check - but that's not something needed for this PR.

CarolEidt · 2018-03-01T11:01:26Z

src/jit/namedintrinsiclist.h

-    // Select base type using argument type
-    HW_Flag_BaseTypeFromArg = 0x400,
+    // Select base type using the first argument type
+    HW_Flag_BaseTypeFromFirstArg = 0x400,


Speaking of asserts (which we were a few hours ago on another thread), this seems like something that could be asserted somewhere - e.g. a pass over the table that validates these kinds of properties. There are probably other consistency checks across signature, category and flag that could be checked.

CarolEidt · 2018-03-01T11:03:31Z

src/jit/namedintrinsiclist.h

+    HW_Flag_SpecialCodeGen = 0x20000,
+
    // No Read/Modify/Write Semantics
    // the intrinsic does not have read/modify/write semantics and doesn't need


This is pre-existing, but this comment isn't complete.
I would qualify it with "the intrinsic doesn't have read/modify/write semantics in two-operand form." (or non-AVX, or whatever the appropriate characterization is).

CarolEidt · 2018-03-01T11:08:04Z

src/jit/hwintrinsicxarch.cpp

        case InstructionSet_SSE:
        case InstructionSet_SSE3:
        case InstructionSet_SSSE3:
+        case InstructionSet_SSE41:


One more moved to the happy state! :-)

CarolEidt · 2018-03-01T11:33:52Z

src/jit/hwintrinsicxarch.cpp

+//    flags   - flags of the intrinsics
+//
+// Return Value:
+//    On 32-bit platforms, return true if the intrinsic does not use any 64-bit registers (r64)


This description doesn't reflect the name or the real purpose. I think it should say:

// Return Value: // Returns true iff the given type signature is supported // // Notes: // - This is only used on 32-bit systems to determine whether the signature uses no 64-bit registers. // - The `retType` is passed to avoid another call to the type system, as it has already been retrieved.

CarolEidt · 2018-03-01T11:36:01Z

src/jit/hwintrinsicxarch.cpp

    if (impIsTableDrivenHWIntrinsic(category, flags))
    {
-        if (!varTypeIsSIMD(retType) || ((flags & HW_Flag_BaseTypeFromArg) != 0))
+        if (category == HW_Category_MemoryStore ||


This expression needs more parentheses to be fully-parenthesized.

CarolEidt · 2018-03-01T11:36:41Z

src/jit/hwintrinsicxarch.cpp

-                assert(category == HW_Category_MemoryStore);
-                baseType =
-                    getBaseTypeOfSIMDType(info.compCompHnd->getArgClass(sig, info.compCompHnd->getArgNext(sig->args)));
+                assert(category == HW_Category_MemoryStore || ((flags & HW_Flag_BaseTypeFromSecondArg) != 0));


This also needs more parens.

fiigii · 2018-03-01T21:18:34Z

src/jit/lsraxarch.cpp

            assert(numArgs != 1);

-            if (info->srcCount >= 2)
+            if (info->srcCount >= 2 && (genActualType(intrinsicTree->TypeGet()) == genActualType(op2->TypeGet())))


@tannergooding I think we can have a stricter check to avoid handling special cases like Insert.

Never mind, we cannot have this check.

fiigii · 2018-03-02T00:29:04Z

test Windows_NT x64 Checked jitincompletehwintrinsic
test Windows_NT x64 Checked jitx86hwintrinsicnoavx
test Windows_NT x64 Checked jitx86hwintrinsicnoavx2
test Windows_NT x64 Checked jitx86hwintrinsicnosimd
test Windows_NT x64 Checked jitnox86hwintrinsic

test Windows_NT x86 Checked jitincompletehwintrinsic
test Windows_NT x86 Checked jitx86hwintrinsicnoavx
test Windows_NT x86 Checked jitx86hwintrinsicnoavx2
test Windows_NT x86 Checked jitx86hwintrinsicnosimd
test Windows_NT x86 Checked jitnox86hwintrinsic

test Ubuntu x64 Checked jitincompletehwintrinsic
test Ubuntu x64 Checked jitx86hwintrinsicnoavx
test Ubuntu x64 Checked jitx86hwintrinsicnoavx2
test Ubuntu x64 Checked jitx86hwintrinsicnosimd
test Ubuntu x64 Checked jitnox86hwintrinsic

test OSX10.12 x64 Checked jitincompletehwintrinsic
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx2
test OSX10.12 x64 Checked jitx86hwintrinsicnosimd
test OSX10.12 x64 Checked jitnox86hwintrinsic

fiigii · 2018-03-02T00:56:36Z

CI seems to have some IO problems. All tests passed on my local machines.

fiigii · 2018-03-02T00:57:30Z

@tannergooding @CarolEidt Addressed all the feedback, does the current code look good to you?

tannergooding · 2018-03-02T00:58:33Z

CC. @dotnet/dnceng, are the Mac machines in some bad state?

tannergooding · 2018-03-02T00:59:54Z

src/jit/emitxarch.cpp

+    if ((ins == INS_pextrq || ins == INS_pinsrq) && !UseVEXEncoding())
+    {
+        assert(UseSSE4());
+        sz += 1;


separate issue: We really need to cleanup the code size estimation code (CC. @CarolEidt).

Yeah, let me just remind you that mis-estimates can lead to odd CHK/RET codegen diffs (#13399).

4creators · 2018-03-02T01:00:34Z

I have logged issue #16696 due to failing OSX jobs

mmitche · 2018-03-02T01:01:20Z

@tannergooding I think there is something wrong in the lab. This is happening across multiple jenkins instances.

tannergooding · 2018-03-02T01:02:34Z

src/jit/hwintrinsiccodegenxarch.cpp


    switch (intrinsicID)
    {
-        case NI_SSE_ConvertScalarToVector128Single:


Just to confirm. This is now considered table driven, correct?

tannergooding · 2018-03-02T01:06:37Z

src/jit/lsraxarch.cpp

+        case NI_SSE41_Extract:
+            if (baseType == TYP_FLOAT)
+            {
+                info->internalIntCount += 1;


Should we explicitly set the internal candidates, as we have done elsewhere?

No necessary, this internal register can be any GPR.

tannergooding

This looks reasonable to me overall.

I would like to spend some time cleaning up this code (as it is a bit messy right now) after we get the currently approved intrinsics in.

fiigii · 2018-03-02T01:10:43Z

I would like to spend some time cleaning up this code

Don't you mean to clean up the code-size estimation code?

tannergooding · 2018-03-02T01:12:54Z

Don't you mean to clean up the code-size estimation code?

I meant the intrinsic code in general. I've gone over it a couple times and it looks like there is some room for cleanup/improvement in a few places.

CarolEidt · 2018-03-02T05:58:40Z

test OSX10.12 x64 Checked jitincompletehwintrinsic
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx2
test OSX10.12 x64 Checked jitx86hwintrinsicnosimd
test OSX10.12 x64 Checked jitnox86hwintrinsic

CarolEidt · 2018-03-02T05:59:10Z

test OSX10.12 x64 Checked Innerloop Build and Test

fiigii · 2018-03-02T08:44:31Z

Can we merge this PR?

CarolEidt · 2018-03-02T14:40:59Z

Can we merge this PR?

I will go ahead and merge. I think the odds of breaking something on OSX with this change but not the other OS's is pretty small.

CarolEidt · 2018-03-02T19:44:19Z

It seems that we had a bad merge with PR #16669. @fiigii @tannergooding could one of you ensure consistent use of HW_Flag_BaseTypeFromArg and HW_Flag_BaseTypeFromFirstArg / HW_Flag_BaseTypeFromSecondArg? SSE2_MaskMove is using the former.

fiigii · 2018-03-02T19:49:17Z

@CarolEidt I have changed HW_Flag_BaseTypeFromArg to HW_Flag_BaseTypeFromFirstArg, let me fix SSE2_MaskMove. Thank you.

fiigii commented Feb 28, 2018

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tannergooding reviewed Feb 28, 2018

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fiigii force-pushed the insertextract branch 2 times, most recently from 87b2e82 to 556065f Compare February 28, 2018 11:33

fiigii changed the title ~~Update the table-driven framework and simplify SSE/SSE2 intrinsic~~ Implement SSE4.1 Insert/Extract and simplify SSE/SSE2 intrinsic Feb 28, 2018

fiigii force-pushed the insertextract branch from 556065f to 81961d1 Compare February 28, 2018 22:09

fiigii commented Feb 28, 2018

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fiigii mentioned this pull request Feb 28, 2018

Implement Shuffle* Sse2 Intel hardware intrinsics #15777

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fiigii force-pushed the insertextract branch from 81961d1 to def1ff2 Compare March 1, 2018 00:43

tannergooding reviewed Mar 1, 2018

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CarolEidt suggested changes Mar 1, 2018

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FeiPengIntel added 2 commits March 1, 2018 11:27

Add tests and templates for insert/extract

1536bcc

Update 64-bit intrinsics and simplify SSE/SSE2 intrinsic

d7a5bb9

fiigii force-pushed the insertextract branch from def1ff2 to 04035e5 Compare March 1, 2018 21:15

fiigii commented Mar 1, 2018

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Implement SSE4.1 insert and extract

c767b4d

fiigii force-pushed the insertextract branch from 04035e5 to c767b4d Compare March 1, 2018 21:45

tannergooding reviewed Mar 2, 2018

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tannergooding approved these changes Mar 2, 2018

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CarolEidt approved these changes Mar 2, 2018

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CarolEidt merged commit 1116aa7 into dotnet:master Mar 2, 2018

fiigii mentioned this pull request Mar 2, 2018

Fix a bad marge #16715

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sandreenko mentioned this pull request Mar 4, 2018

fix desktop legacy backend failures #16741

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fiigii commented Feb 28, 2018 •

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tannergooding Mar 2, 2018 •

edited

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