-
Notifications
You must be signed in to change notification settings - Fork 565
virtio-devices: iommu: allow limiting maximum address width in bits #6900
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
virtio-devices: iommu: allow limiting maximum address width in bits #6900
Conversation
84ad1ae to
fb89231
Compare
tests/integration.rs
Outdated
| .args(["--memory", "size=4G"]) | ||
| .args(["--kernel", fw_path(FwType::RustHypervisorFirmware).as_str()]) | ||
| .args(["--device", format!("path={NVIDIA_VFIO_DEVICE}").as_str()]) | ||
| .args(["--platform", "iommu_address_width=42"]) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I don't think this test will have a virtio-iommu device as that is only added if any device has iommu=on
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Good catch!
Should I keep the test, modifying it to use iommu=on, or have it somewhere else where it's more appropriate in the test suite?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Added iommu=on, but not sure if the host running this test is actually configured to support this option.
7d9bb66 to
d6d5c69
Compare
d6d5c69 to
4e05c8f
Compare
|
Force-pushed to fix the formatting. |
|
Is it possible to break down the single commit into multiple like below?
|
@russell-islam would you mind sharing your rationale behind this? The PR itself is pretty small ( |
Typically we try to separate the changes to each crate/components if it is in dependent. It's fine if the commit is small. In the commit we always try to follow the format crate: commit message. At least I got these type of impression before for my PRs. |
@russell-islam please take a look at change for It's inherently related to the "main changes", because What would be the point of splitting this into a separate commit? |
Just add a tiny commit for this. That's okay. Then make another commit for test related changes. Please try to see if the following split is possible.
It's okay to have small commits with independent changes. |
4e05c8f to
7d6efea
Compare
I've performed the split and force pushed the changes, please take a look.
I agree, but fuzz changes, for example, are dependent on virtio-devices changes (signature change), yet you ask to split them 🤷 |
If the fuzz changes are tightly dependent on the virtio device changes (due to function signature changes) then you were correct to merge them. The CI checks that each commit is independently compilable (however I don't think it spans across the the main and separate fuzz workspace.) |
7d6efea to
38b38e1
Compare
Force pushed a new set of commits. |
Thats fine. |
russell-islam
left a comment
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
| SeccompAction::Allow, | ||
| EventFd::new(EFD_NONBLOCK).unwrap(), | ||
| ((MEM_SIZE - IOVA_SPACE_SIZE) as u64, (MEM_SIZE - 1) as u64), | ||
| 64, |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Use something like, const MAX_IOMMU_ADDRESS_WIDTH_BITS: u8 = 64;
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Since you've asked me to split the commits above, and @rbradford stated that commits should be independently compilable (atomic), this would not be possible to achieve because:
virtio-devices: iommu: allow limiting maximum address width in bitscontains this linevmm: introduce platform option to limit maximum IOMMU address widthcontains theMAX_IOMMU_ADDRESS_WIDTH_BITSconstant
|
Please rebase these changes and force push - I want to ensure we're running atop the latest tree as there have been some changes related to the kernel CI. |
Signed-off-by: Nikolay Edigaryev <[email protected]>
Currently, Cloud Hypervisor does not set a VIRTIO_IOMMU_F_INPUT_RANGE
feature bit for the VirtIO IOMMU device, which, according to spec[1],
means that the guest may use the whole 64-bit address space is for
IOMMU purposes:
>If the feature is not offered, virtual mappings span over the whole
>64-bit address space (start = 0, end = 0xffffffff ffffffff)
As far as I am aware, there are currently no host platforms on
the market capable of addressing the whole 64-bit address space.
For example, I am currently working with a host platform that reports
39-bit address space for IOMMU purposes:
>DMAR: Host address width 39
When running a VFIO pass-through guest on such a platform, NVIDIA
driver in guest gets DMA mapping failures when working with large data,
and this results in Cloud Hypervisor exiting with the following error:
>cloud-hypervisor: 1501.220535s: <__iommu>
>ERROR:virtio-devices/src/thread_helper.rs:53 -- Error running worker:
>HandleEvent(Failed to process request queue : ExternalMapping(Custom
>{ kind: Other, error: "failed to map memory for VFIO container, iova
>0x7fff00000000, gpa 0x24ce25000, size 0x1000: IommuDmaMap(Error(22))"
>}))
Passing "--platform iommu_address_width=39" to Cloud Hypervisor built
with this change fixes this.
[1]: https://docs.oasis-open.org/virtio/virtio/v1.3/csd01/
virtio-v1.3-csd01.html#x1-5420006
Signed-off-by: Nikolay Edigaryev <[email protected]>
38b38e1 to
31c3780
Compare
@rbradford done 👌 |
rbradford
left a comment
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I was going to ask if 64 bits is a sensible default - and what QEMU does. I can see that QEMU defaults to 64-bits too.
|
@edigaryev Your newly added test failed - I think it's because there is no |
31c3780 to
f8aa0e5
Compare
|
@rbradford thanks for the heads up and a good catch! I've updated the test in f8aa0e5 to additionally specify |
Signed-off-by: Nikolay Edigaryev <[email protected]>
Head branch was pushed to by a user without write access
f8aa0e5 to
957f4ea
Compare
|
Fixed code formatting for test. |
Yes - this is an issue with beta clippy - rust-lang/rust-clippy#13953 affecting all our PRs. I've not disabled beta as I think (hope?) this will be backporting soon. Failures of clippy beta does not block merging. |
5a8df36
Currently, Cloud Hypervisor does not set a VIRTIO_IOMMU_F_INPUT_RANGE feature bit for the VirtIO IOMMU device, which, according to spec, means that the guest may use the whole 64-bit address space is for IOMMU purposes:
As far as I am aware, there are currently no host platforms on the market capable of addressing the whole 64-bit address space.
For example, I am currently working with a host platform that reports 39-bit address space for IOMMU purposes:
When running a VFIO pass-through guest on such a platform, NVIDIA driver in guest gets DMA mapping failures when working with large data, and this results in Cloud Hypervisor exiting with the following error:
Passing
--platform iommu_address_width=39to Cloud Hypervisor built with this change fixes this.