[core] Add Temporal inline layer, trait #5018
Merged
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Add a new
Temporalinline layers that are nested under each of thebuiltin Assert, Assume, and Cover layers. These layers exist because we
have observed situations where assertions which should be legal in all
designs are unsupported by specific tools, though they are legal
properties by the SystemVerilog spec.
E.g.,
s_eventuallyis entirely unsupported by Verilator and has onlylimited support in VCS. The motivation for this PR is to have a location
where we can put these assertions and guard them off with tools that do
not support them.
Because this is expected to be problematic for all of the existing builtin
layers, this is added to each of Assert, Assume, and Cover. Additionally,
as users have user-defined layers, the pattern of creating this
Temporallayer is factored into a trait,
HasTemporalInlineLayerso that it can bereused by others.
Release Notes
Temporallayer under each of the builtinAssert,Assume, andCoverlayers. This is intended to be used to guard complex or unsupportedproperties due to spotty simulator support.
HasTemporalInlineLayertrait to allow users to easily add a recognizableTemporalchild layer to their user-defined layers.