[core] Switch to FIRRTL 6.0.0 inline layer ABI (#4982)

seldridge · chiselbot · commit 121c08e4e886 · 2025-07-22T11:06:26.000Z
The forthcoming FIRRTL 6.0.0 makes some changes to the ABI for inline layers [[1]]. Specifically, the module name was dropped and the delimiter _after_ "layer" was changed from '_' to '$'. E.g., what was previously: ``` layer_Foo$A ``` Is now: ``` layer$A ``` Propagate this change into Chisel by updating the way that inline layers self-report their ABI. This is needed to keep Chisel compatible with CIRCT 1.126.0. [1]: chipsalliance/firrtl-spec@b88817b Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
diff --git a/core/src/main/scala/chisel3/Layer.scala b/core/src/main/scala/chisel3/Layer.scala
@@ -52,7 +52,7 @@ object layer {
 
       /** Return the macro identifier that should be defined. */
       def toMacroIdentifier(layer: Layer, circuitName: String): String = {
-        (s"layer_$circuitName" +: layer.layerSeq.map(_.name)).mkString("$")
+        ("layer" +: layer.layerSeq.map(_.name)).mkString("$")
       }
 
     }
diff --git a/docs/src/explanations/layers.md b/docs/src/explanations/layers.md
@@ -208,17 +208,17 @@ only a child layer's file will automatically include its parent layer's file.
 
 Inline layers have their layer blocks guarded with conditional compilation
 directives.  To enable an inline layer, set a preprocessor define when compiling
-your design.  The preprocessor define begins with `layer_` and then includes the
-circuit name and all layer names delimited with dollar signs (`$`).  Parent
-extract layer names appear in the macro.
+your design.  The preprocessor define begins with `layer$` and then includes the
+all layer names delimited with dollar signs (`$`).  Parent extract layer names
+appear in the macro.
 
 For example, for module `Foo` declared above, this will be sensitive to three
 macros, one for each inline layer:
 
 ```
-layer_Foo$B
-layer_Foo$C$E
-layer_Foo$C$E$F
+layer$B
+layer$C$E
+layer$C$E$F
 ```
 
 ## User-defined Layers
@@ -487,7 +487,7 @@ the bind file, `layers-Foo-A.sv`.
 
 The design below is the same as the previous example, but uses an inline layer.
 Based on the FIRRTL ABI, we can expect that the body of the layer block will be
-guarded by an `` `ifdef `` sensitive to the preprocessor macro `layer_Foo$A`.
+guarded by an `` `ifdef `` sensitive to the preprocessor macro `layer$A`.
 
 ```scala mdoc:reset:silent
 import chisel3._
@@ -593,7 +593,7 @@ following filenames.  One file is created for each extract layer:
 1. `layers_Foo_Verification_Assert.sv`
 
 Additionally, the resulting SystemVerilog will be sensitive to the preprocessor
-define `layer_Foo$Verification$Debug` due to the one inline layer we added.
+define `layer$Verification$Debug` due to the one inline layer we added.
 
 A user can then include any combination of these files in their design to
 include the optional functionality described by the `Verification` or
diff --git a/src/test/scala-2/chiselTests/LayerSpec.scala b/src/test/scala-2/chiselTests/LayerSpec.scala
@@ -572,9 +572,9 @@ class LayerSpec extends AnyFlatSpec with Matchers with FileCheck {
          |CHECK:      module Foo_A(
          |CHECK-NOT:    `ifdef
          |CHECK:        foo: assert property
-         |CHECK:        `ifdef layer_Foo$A$B
+         |CHECK:        `ifdef layer$A$B
          |CHECK-NEXT:     bar: assert property
-         |CHECK-NEXT:     `ifdef layer_Foo$A$B$C
+         |CHECK-NEXT:     `ifdef layer$A$B$C
          |CHECK-NEXT:       baz: assert property
          |CHECK-NEXT:     `endif
          |CHECK-NEXT:   `endif""".stripMargin

Original file line number	Diff line number	Diff line change
`@@ -52,7 +52,7 @@ object layer {`
`52`	`52`
`53`	`53`	`/** Return the macro identifier that should be defined. */`
`54`	`54`	`def toMacroIdentifier(layer: Layer, circuitName: String): String = {`
`55`		`- (s"layer_$circuitName" +: layer.layerSeq.map(_.name)).mkString("$")`
	`55`	`+ ("layer" +: layer.layerSeq.map(_.name)).mkString("$")`
`56`	`56`	`}`
`57`	`57`
`58`	`58`	`}`