@@ -311,16 +311,6 @@ static inline void dwc2_chan_transfer(struct usbh_bus *bus, uint8_t ch_num, uint
311311 (((uint32_t )num_packets << 19 ) & USB_OTG_HCTSIZ_PKTCNT ) |
312312 (((uint32_t )pid << 29 ) & USB_OTG_HCTSIZ_DPID );
313313
314- if (!(ep_addr & 0x80 )) {
315- if (buf ) {
316- usb_dcache_clean ((uintptr_t )buf , USB_ALIGN_UP (size , CONFIG_USB_ALIGN_SIZE ));
317- }
318- } else {
319- if (buf ) {
320- usb_dcache_invalidate ((uintptr_t )buf , USB_ALIGN_UP (size , CONFIG_USB_ALIGN_SIZE ));
321- }
322- }
323-
324314 /* xfer_buff MUST be 32-bits aligned */
325315 USB_OTG_HC (ch_num )-> HCDMA = (uint32_t )buf ;
326316
@@ -1066,6 +1056,25 @@ int usbh_submit_urb(struct usbh_urb *urb)
10661056
10671057 usb_osal_leave_critical_section (flags );
10681058
1059+ if (urb -> setup ) {
1060+ usb_dcache_clean ((uintptr_t )urb -> setup , USB_ALIGN_UP (sizeof (struct usb_setup_packet ), CONFIG_USB_ALIGN_SIZE ));
1061+
1062+ if (urb -> transfer_buffer ) {
1063+ if (urb -> setup -> bmRequestType & 0x80 ) {
1064+ usb_dcache_invalidate ((uintptr_t )urb -> transfer_buffer , USB_ALIGN_UP (urb -> transfer_buffer_length , CONFIG_USB_ALIGN_SIZE ));
1065+ } else {
1066+ usb_dcache_clean ((uintptr_t )urb -> transfer_buffer , USB_ALIGN_UP (urb -> transfer_buffer_length , CONFIG_USB_ALIGN_SIZE ));
1067+ }
1068+ }
1069+ } else if (urb -> transfer_buffer && (USB_GET_ENDPOINT_TYPE (urb -> ep -> bmAttributes ) != USB_ENDPOINT_TYPE_ISOCHRONOUS )) {
1070+ if (urb -> ep -> bEndpointAddress & 0x80 ) {
1071+ usb_dcache_invalidate ((uintptr_t )urb -> transfer_buffer , USB_ALIGN_UP (urb -> transfer_buffer_length , CONFIG_USB_ALIGN_SIZE ));
1072+ } else {
1073+ usb_dcache_clean ((uintptr_t )urb -> transfer_buffer , USB_ALIGN_UP (urb -> transfer_buffer_length , CONFIG_USB_ALIGN_SIZE ));
1074+ }
1075+ } else {
1076+ }
1077+
10691078 switch (USB_GET_ENDPOINT_TYPE (urb -> ep -> bmAttributes )) {
10701079 case USB_ENDPOINT_TYPE_CONTROL :
10711080 chan -> ep0_state = DWC2_EP0_STATE_SETUP ;
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