s390x: Improved TrapIf implementation#6079
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alexcrichton merged 1 commit intobytecodealliance:mainfrom Mar 23, 2023
Merged
s390x: Improved TrapIf implementation#6079alexcrichton merged 1 commit intobytecodealliance:mainfrom
alexcrichton merged 1 commit intobytecodealliance:mainfrom
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alexcrichton
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Mar 21, 2023
| // of the branch (BRCL) instruction itself - those middle two bytes | ||
| // are zero, which matches the trap instruction itself. | ||
| let opcode = 0xc04; // BCRL | ||
| let enc = &enc_ril_c(opcode, cond.bits(), 2); |
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Could this add some assertions that enc has length 6 and the middle 2 bytes are zeros?
| let cond = cond.invert().pretty_print_default(); | ||
| format!("j{} 6 ; trap", cond) | ||
| let cond = cond.pretty_print_default(); | ||
| format!("jg{} .+2", cond) |
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Like the other backends (which Jamey suggested and I think is a good idea), could this include the trap code in the printing? The other backends do something like # trap={code} at the end IIRC
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Indeed, good idea. I've also added this for the unconditional traps now.
Following up on the discussion in bytecodealliance#6011 this adds an improved implementation of TrapIf for s390x using a single conditional branch instruction. If the trap conditions is true, we branch into the middle of the branch instruction - those middle two bytes are zero, which matches the encoding of the trap instruction. In addition, show the trap code for Trap and TrapIf instructions in assembler output.
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Following up on the discussion in
#6011 this adds an improved implementation of TrapIf for s390x using a single conditional branch instruction.
If the trap conditions is true, we branch into the middle of the branch instruction - those middle two bytes are zero, which matches the encoding of the trap instruction.