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x64: Incorrect codegen for f32x4.abs v128.not #3327
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bugIncorrect behavior in the current implementation that needs fixingIncorrect behavior in the current implementation that needs fixingcranelift:area:x64Issues related to x64 codegenIssues related to x64 codegenfuzz-bugBugs found by a fuzzerBugs found by a fuzzerwasm-proposal:simdIssues related to the WebAssembly SIMD proposalIssues related to the WebAssembly SIMD proposal
Description
Found via fuzzing this module:
(module
(func (result v128)
v128.const f32x4 0 0 0 0
f32x4.abs
v128.not)
(export "1" (func 0))
)yields:
$ cargo run testcase0.wat --invoke 1 --enable-simd
warning: using `--invoke` with a function that returns values is experimental and may break in the future
0
when it should print u128::MAX.
The disassembly of this function is:
0000000000000000 <_wasm_function_0>:
0: 55 push %rbp
1: 48 89 e5 mov %rsp,%rbp
4: f3 0f 6f 05 24 00 00 movdqu 0x24(%rip),%xmm0 # 30 <_wasm_function_0+0x30>
b: 00
c: 0f 57 c9 xorps %xmm1,%xmm1
f: 0f c2 c9 00 cmpeqps %xmm1,%xmm1
13: 66 0f 72 d1 01 psrld $0x1,%xmm1
18: 0f 54 c1 andps %xmm1,%xmm0
1b: 0f c2 c9 00 cmpeqps %xmm1,%xmm1
1f: 0f 57 c1 xorps %xmm1,%xmm0
22: 48 89 ec mov %rbp,%rsp
25: 5d pop %rbp
26: c3 retq
I don't for sure know what's going on here with each individual instruction, but this sort of looks like a register allocator issue? I'm not sure what the second xorps is doing there with those registers. If this is a register allocator thing it may or may not be related to #3216
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bugIncorrect behavior in the current implementation that needs fixingIncorrect behavior in the current implementation that needs fixingcranelift:area:x64Issues related to x64 codegenIssues related to x64 codegenfuzz-bugBugs found by a fuzzerBugs found by a fuzzerwasm-proposal:simdIssues related to the WebAssembly SIMD proposalIssues related to the WebAssembly SIMD proposal