Support RISC-V target in new backend framework #2217
Description
As mentioned in a reddit discussion here, we don't yet have a tracking issue for this.
We should implement a backend in the MachInst framework for RISC-V 32- and/or 64-bit platforms. It seems we had the very start of this in the old backend framework (cranelift/codegen/src/isa/riscv/) but it appears fairly skeletal.