Record: Allow to configure Perf Events based on Model #112
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| static BACKEND_STALLS: NamedTypeCtr = NamedTypeCtr { | ||
| perf_type: PerfType::RAW, | ||
| name: "Backend-Stalls", | ||
| config: 0x10a2, |
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correcting a bug too? I didn't see it mentioned in commit message.
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Added it to the commit.
src/data.rs
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| pub mod flamegraphs; | ||
| #[cfg(target_arch = "aarch64")] | ||
| pub mod grv_perf_events; | ||
| pub mod intel_icelake_perf_events; |
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this should go after line 8 below.
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Yeah. Changing this as it should only be compiled on x86. rustfmt moved these :( .
src/data.rs
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| pub mod grv_perf_events; | ||
| pub mod intel_icelake_perf_events; | ||
| #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] | ||
| pub mod intel_perf_events; |
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can you add a comment as to which Intel architecture does this file apply to?
| @@ -0,0 +1,40 @@ | |||
| use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType}; | |||
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| static CYCLES: NamedTypeCtr = NamedTypeCtr { | |||
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These are same as the default in intel_perf_events.rs. So, does this architecture specific config file provide delta counters or all?
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We make sure the nr and dr are in the same file. We don't want to refer to other files for a PMU event.
RamaMalladiGH
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RamaMalladiGH
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General comments, 1 change request.
Also, fix a bug in the default Intel PMU config for Backend Stalls.
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Icelake and Sapphire Rapids have different configurations for the PMU events. Change them based on the Model during run-time.
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