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JackyBaicdleonard
JackyBai
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cdleonard
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MLK-16266-02 ARM: imx: Enhance the code to support new TO for imx6qp
Previous code don't take care about the i.MX6QP revision update of new TO. So improve the code to include future TO support for i.MX6QP. Signed-off-by: Bai Ping <[email protected]>
1 parent cf6fa14 commit 513e1c9

5 files changed

Lines changed: 16 additions & 13 deletions

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‎arch/arm/mach-imx/anatop.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ void imx_anatop_pre_suspend(void)
146146
return;
147147
}
148148

149-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
149+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
150150
imx_anatop_disable_pu(true);
151151

152152
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
@@ -176,7 +176,7 @@ void imx_anatop_post_resume(void)
176176
return;
177177
}
178178

179-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
179+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
180180
imx_anatop_disable_pu(false);
181181

182182
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||

‎arch/arm/mach-imx/cpu.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ struct device * __init imx_soc_device_init(void)
126126
soc_id = "i.MX6SX";
127127
break;
128128
case MXC_CPU_IMX6Q:
129-
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
129+
if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
130130
soc_id = "i.MX6QP";
131131
else
132132
soc_id = "i.MX6Q";

‎arch/arm/mach-imx/gpc.c‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*
22
* Copyright 2011-2016 Freescale Semiconductor, Inc.
33
* Copyright 2011 Linaro Ltd.
4+
* Copyright 2017 NXP.
45
*
56
* The code contained herein is licensed under the GNU General Public
67
* License. You may obtain a copy of the GNU General Public License
@@ -231,7 +232,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
231232
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
232233
int i;
233234

234-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
235+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
235236
_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
236237

237238
/* power down the mega-fast power domain */
@@ -254,7 +255,7 @@ void imx_gpc_post_resume(void)
254255
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
255256
int i;
256257

257-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
258+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
258259
_imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
259260

260261
/* Keep ARM core powered on for other low-power modes */
@@ -648,7 +649,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
648649
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
649650

650651
if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() &&
651-
imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
652+
imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
652653
return 0;
653654

654655
_imx6q_pm_pu_power_off(genpd);
@@ -693,7 +694,7 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
693694
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
694695
int ret;
695696

696-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0
697+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0
697698
&& &imx6q_pu_domain == pu) {
698699
if (!pu_on)
699700
pu_on = true;
@@ -856,7 +857,7 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
856857

857858
is_off = IS_ENABLED(CONFIG_PM);
858859
if (is_off && !(cpu_is_imx6q() &&
859-
imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)) {
860+
imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)) {
860861
_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
861862
} else {
862863
/*

‎arch/arm/mach-imx/mach-imx6q.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*
22
* Copyright 2011-2015 Freescale Semiconductor, Inc.
33
* Copyright 2011 Linaro Ltd.
4+
* Copyright 2017 NXP.
45
*
56
* The code contained herein is licensed under the GNU General Public
67
* License. You may obtain a copy of the GNU General Public License
@@ -310,15 +311,15 @@ static inline void imx6q_enet_init(void)
310311
imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp");
311312
imx6q_enet_phy_init();
312313
imx6q_1588_init();
313-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
314+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
314315
imx6q_enet_clk_sel();
315316
}
316317

317318
static void __init imx6q_init_machine(void)
318319
{
319320
struct device *parent;
320321

321-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
322+
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
322323
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
323324
else
324325
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",

‎drivers/clk/imx/clk-imx6q.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*
22
* Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
33
* Copyright 2011 Linaro Ltd.
4+
* Copyright 2017 NXP.
45
*
56
* The code contained herein is licensed under the GNU General Public
67
* License. You may obtain a copy of the GNU General Public License
@@ -662,7 +663,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
662663
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
663664
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
664665

665-
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
666+
if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
666667
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
667668
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
668669
} else {
@@ -990,7 +991,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
990991
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
991992
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
992993
} else if (clk_on_imx6q()) {
993-
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
994+
if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
994995
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]);
995996
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 720000000);
996997
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
@@ -1087,7 +1088,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
10871088
* for i.MX6QP with speeding grading set to 1.2GHz,
10881089
* VPU should run at 396MHz.
10891090
*/
1090-
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
1091+
if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
10911092
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
10921093
WARN_ON(!np);
10931094

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