RTeAAL Sim

This repository is the open-source artifact for our ASPLOS 2026 paper RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation.

Introduction

RTL simulation on general-purpose CPUs remains a persistent bottleneck in modern hardware design. State-of-the-art simulators, such as Verilator, embed the entire circuit directly into a monolithic simulation binary. While effective, this approach leads to long compilation times and execution that is fundamentally CPU frontend-bound, suffering from significant instruction-cache pressure.

RTeAAL Sim reformulates cycle-accurate RTL simulation as a sparse tensor algebra problem. Instead of hardwiring the circuit structure into compiled control flow, RTeAAL Sim:

• Represents RTL circuits as sparse tensors
• Expresses simulation as sparse tensor algebra kernels
• Decouples simulation behavior from binary size
• Enables the use of well-studied tensor algebra optimizations

Source Code Overview

This repository comprises the following components:

.
├── benchmark/    # RISC-V benchmark binaries used in evaluation
├── experiments/  # Scripts for running experiments and collecting results
├── kernel/       # RTeAAL Sim's C++ sparse tensor algebra simulation kernels
├── src/          # Scala compiler: generates sparse tensor files from FIRRTL
├── utils/        # Utility scripts for extracting memory instance metadata
├── verilator/    # Build scripts for Verilator simulators (baseline)
└── essent/       # Build scripts for ESSENT simulators (baseline)

Prerequisites

• Java 8 / SBT — for compiling the Scala-based RTeAAL Sim compiler (tested with OpenJDK 1.8.0, SBT runner 1.11.0)
• clang++ — for compiling the C++ simulation kernels (C++17)
• Python 3 — for utility scripts in utils/
• FIRRTL design files — input .fir files must be generated separately; see Obtaining RTL Design Files below
• Linux OS is required for running simulation

Obtaining RTL Design Files

The FIRRTL and Verilog files for the evaluated designs (RocketChip, BOOM, Gemmini, SHA3) are large, and most of them are not included in this repository. FIRRTL files are generated by wrapping each RTL design with RocketChip IO and debug ports, following the flow described in boom-standalone.

After you get the FIRRTL and Verilog files, place them as follows:

• FIRRTL files → essent/firrtls/
• Verilog files → verilator/verilogs/

As an example, we add the FIRRTL and Verilog file for 8-core RocketChip.

Quick Start

Before building any simulator, compile the fesvr (Front-End Server) library, which loads RISC-V programs onto the simulated RTL design:

cd kernel
make libfesvr.a

Building Simulators

RTeAAL Sim

First, compile the RTeAAL Sim compiler (built on top of ESSENT, uses its frontend FIRRTL parser. Our newly added files can be found under src/main/scala/, all start with "TeAAL"):

cd kernel
make build_jar

Then compile the simulator for a specific design:

make <design>

where <design> is the design name (e.g., rocketchip-1c for a single-core RocketChip).

This step runs the FIRRTL file through the RTeAAL Sim compiler to generate sparse tensor files for the design, then compiles the C++ simulation kernels (e.g., RU, NU, etc.). See kernel/README.md for details on the generated files and kernel variants.

**TODO: Remove the unused ESSENT files, e.g. optimization passes and compiler backend.

Verilator (baseline)

cd verilator
make verilator_install        # fetches and builds Verilator automatically
make compile_verilator_<design>

ESSENT (baseline)

cd essent
make essent_jar
make compile_essent_<design>

Running Simulations

The experiments/ directory contains scripts for running simulations and collecting performance data.

RTeAAL Sim

cd experiments
./RTeAALSim_perf.sh <repeat> <core>

• <repeat>: number of times each configuration is run
• <core>: CPU core ID to pin the simulation to

Configurable parameters inside the script:

• ARGS_DESIGNS: list of RTL designs to simulate
• KERNELS: list of RTeAAL Sim kernel variants to run (e.g., RU, NU)
• BENCHS: list of RISC-V benchmarks to run on each design
• PERF_COMMAND: performance collection command (e.g., time or perf stat)

Verilator and ESSENT (baselines)

cd experiments
./base_perf.sh <verilator|essent> <repeat> <core>

Adding New RTL Designs

• RTeAAL Sim: see kernel/README.md
• Verilator: see verilator/README.md
• ESSENT: see essent/README.md

Citation

If you use this repository in your work, please cite:

@inproceedings{rteaalsim,
    title={RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation},
    author={Yan Zhu and Boru Chen and Christopher W. Fletcher and Nandeeka Nayak},
    year={2026},
    booktitle={ASPLOS}
}