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RED-176382 Fix FT.CREATE failure with LeanVec parameters on non-Intel architectures#7344

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meiravgri merged 2 commits intomasterfrom
meiravg_fix_lvq_check
Nov 12, 2025
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RED-176382 Fix FT.CREATE failure with LeanVec parameters on non-Intel architectures#7344
meiravgri merged 2 commits intomasterfrom
meiravg_fix_lvq_check

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@meiravgri meiravgri commented Nov 12, 2025

VecSim_IsLeanVecCompressionType() was checking both the compression type AND Intel architecture support, causing FT.CREATE commands with valid LeanVec parameters to fail on non-Intel systems during parameter validation.

Solution

  • Simplified VecSim_IsLeanVecCompressionType() to only check if the compression type is LeanVec (removed Intel CPU check)
  • Exposed isLVQSupported() function to check Intel architecture support separately
  • Moved the Intel architecture gating to FT.INFO when displaying reduced_dim field

remove isLVQSupportedfrom VecSim_IsLeanVecCompressionType
expose isLVQSupported

add , 'LeanVec4x8' to test_vecsim_svs:test_svs_vamana_info
meiravgri added a commit that referenced this pull request Nov 12, 2025
@meiravgri meiravgri changed the title RED-176382 move isLVQSupported() to info RED-176382 Fix FT.CREATE failure with LeanVec parameters on non-Intel architectures Nov 12, 2025
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codecov bot commented Nov 12, 2025

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 85.25%. Comparing base (51a37fb) to head (7ea532f).
⚠️ Report is 2 commits behind head on master.

Additional details and impacted files
@@            Coverage Diff             @@
##           master    #7344      +/-   ##
==========================================
- Coverage   85.26%   85.25%   -0.02%     
==========================================
  Files         344      344              
  Lines       53005    53005              
  Branches    13712    13712              
==========================================
- Hits        45194    45187       -7     
- Misses       7616     7623       +7     
  Partials      195      195              
Flag Coverage Δ
flow 84.53% <100.00%> (-0.03%) ⬇️
unit 52.41% <0.00%> (-0.01%) ⬇️

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@meiravgri meiravgri added this pull request to the merge queue Nov 12, 2025
auto-merge was automatically disabled November 12, 2025 17:41

Pull Request is not mergeable

Merged via the queue into master with commit 2c35686 Nov 12, 2025
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@meiravgri meiravgri deleted the meiravg_fix_lvq_check branch November 12, 2025 19:31
redisearch-backport-pull-request bot pushed a commit that referenced this pull request Nov 12, 2025
… architectures (#7344)

* move  isLVQSupported() to info
remove isLVQSupportedfrom VecSim_IsLeanVecCompressionType
expose isLVQSupported

add , 'LeanVec4x8' to test_vecsim_svs:test_svs_vamana_info

* add reduce

(cherry picked from commit 2c35686)
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redisearch-backport-pull-request bot pushed a commit that referenced this pull request Nov 12, 2025
… architectures (#7344)

* move  isLVQSupported() to info
remove isLVQSupportedfrom VecSim_IsLeanVecCompressionType
expose isLVQSupported

add , 'LeanVec4x8' to test_vecsim_svs:test_svs_vamana_info

* add reduce

(cherry picked from commit 2c35686)
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github-merge-queue bot pushed a commit that referenced this pull request Nov 12, 2025
…on-Intel architectures (#7346)

* pr #7344 to 8.4

* revert unrelacted

* another revert
github-merge-queue bot pushed a commit that referenced this pull request Nov 13, 2025
…-Intel architectures (#7350)

RED-176382 Fix FT.CREATE failure with LeanVec parameters on non-Intel architectures (#7344)

* move  isLVQSupported() to info
remove isLVQSupportedfrom VecSim_IsLeanVecCompressionType
expose isLVQSupported

add , 'LeanVec4x8' to test_vecsim_svs:test_svs_vamana_info

* add reduce

(cherry picked from commit 2c35686)

Co-authored-by: meiravgri <[email protected]>
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