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Merged
haukepetersen merged 4 commits into from
Sep 22, 2015
Merged

cpu/stm32l1: optimized and fixed timer driver #3856

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d7cf9b3
cpu/stm32l1: optimized and fixed timer driver
haukepetersen Sep 15, 2015
c7d089d
boards/nucleo-l1: adjusted timer configuration
haukepetersen Sep 15, 2015
92ee5d9
boards/limifrog-v1: adjusted timer configuration
haukepetersen Sep 16, 2015
712a096
boards/nucleo-l1: added xtimer configuration
haukepetersen Sep 22, 2015
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27 changes: 10 additions & 17 deletions boards/limifrog-v1/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand Down Expand Up @@ -46,23 +48,14 @@ extern "C" {
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_IRQ_PRIO 1

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_PRESCALER (32U)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
static const timer_conf_t timer_config[] = {
/* device, RCC bit, IRQ bit */
{TIM5, 3, TIM5_IRQn},
};
/* interrupt routines */
#define TIMER_0_ISR (isr_tim5)
/* number of defined timers */
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
Expand Down
10 changes: 10 additions & 0 deletions boards/nucleo-l1/include/board.h
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,16 @@ extern "C" {
*/
#define F_CPU CLOCK_CORECLOCK

/**
* @name xtimer configuration
* @{
*/
#define XTIMER TIMER_DEV(0)
#define XTIMER_CHAN (0)
#define XTIMER_OVERHEAD (6)
#define XTIMER_BACKOFF (3)
/** @} */

/**
* @name Define the UART to be used as stdio and its baudrate
* @{
Expand Down
41 changes: 10 additions & 31 deletions boards/nucleo-l1/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand All @@ -45,37 +47,14 @@ extern "C" {
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_PRESCALER (32U)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0

/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_CHANNELS 4
#define TIMER_1_PRESCALER (32U)
#define TIMER_1_MAX_VALUE (0xffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
static const timer_conf_t timer_config[] = {
/* device, RCC bit, IRQ bit */
{TIM5, 3, TIM5_IRQn},
};
/* interrupt routines */
#define TIMER_0_ISR (isr_tim5)
/* number of defined timers */
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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@A-Paul A-Paul Sep 15, 2015

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A division for every time referencing a constant value?

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@jnohlgard jnohlgard Sep 15, 2015

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The constant will be computed by the compiler at compile time, there won't
be a division at run time.
On Sep 15, 2015 8:18 PM, "A-Paul" [email protected] wrote:

In boards/nucleo-l1/include/periph_conf.h
#3856 (comment):

-#define TIMER_1_MAX_VALUE (0xffff)
-#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
-#define TIMER_1_ISR_0 isr_tim4
-#define TIMER_1_ISR_1 isr_tim5
-#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
-#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
-#define TIMER_1_IRQ_PRIO 1
-#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
+static const timer_conf_t timer_config[] = {

  • /* device, RCC bit, IRQ bit */
  • {TIM5, 3, TIM5_IRQn},
    +};
    +/* interrupt routines /
    +#define TIMER_0_ISR (isr_tim5)
    +/     number of defined timers */
    +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))

A division for every time referencing a constant value?

—
Reply to this email directly or view it on GitHub
https://github.com/RIOT-OS/RIOT/pull/3856/files#r39546009.

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@haukepetersen haukepetersen Sep 16, 2015

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exactly :-)

/** @} */

/**
Expand Down
10 changes: 9 additions & 1 deletion cpu/stm32l1/include/periph_cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@
#define PERIPH_CPU_H_

#include "cpu.h"
#include "periph/dev_enums.h"

#ifdef __cplusplus
extern "C" {
Expand Down Expand Up @@ -81,6 +80,15 @@ typedef enum {
GPIO_AF14 /**< use alternate function 14 */
} gpio_af_t;

/**
* @brief Timer configuration data structure
*/
typedef struct {
TIM_TypeDef *dev; /**< timer device */
uint8_t rcc; /**< bit in the RCC register */
uint8_t irqn; /**< IRQ vector entry number */
} timer_conf_t;

/**
* @brief declare needed generic SPI functions
* @{
Expand Down
5 changes: 1 addition & 4 deletions cpu/stm32l1/include/stm32l1xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -852,10 +852,7 @@ typedef struct
uint16_t RESERVED10; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
uint32_t RESERVED12; /*!< Reserved, 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t CCR[4]; /*!< TIM capture/compare registers 1-4, Address offset: 0x34 ++ */
uint32_t RESERVED17; /*!< Reserved, 0x44 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED18; /*!< Reserved, 0x4A */
Expand Down
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