cpu/stm32f4: Fix SPI baud rate control settings#2315
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haukepetersen merged 3 commits intoRIOT-OS:masterfrom Jan 16, 2015
Merged
cpu/stm32f4: Fix SPI baud rate control settings#2315haukepetersen merged 3 commits intoRIOT-OS:masterfrom
haukepetersen merged 3 commits intoRIOT-OS:masterfrom
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fnack
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Type: bug
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Author
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Would be great if someone (@PeterKietzmann, @haukepetersen) could test this with a logic analyzer for one SPI on APB1 and one on APB2. |
Member
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Whoops, that must have been my fault. I'll test this! |
Member
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I tested the speed values for both ports. Now they're correct. Nice you found this. ACK |
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ACK also from my side -> and go. |
haukepetersen
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cpu/stm32f4: Fix SPI baud rate control settings
jnohlgard
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Jan 19, 2015
The delays were introduced in an attempt to fix "inexplicable timing errors", although the errors were in the SPI bus driver rather than the nrf24l01p driver. See also: - RIOT-OS#1704 - RIOT-OS#2315 Signed-off-by: Joakim Gebart <[email protected]>
jnohlgard
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Jan 19, 2015
The delays were introduced in an attempt to fix "inexplicable timing errors", although the errors were in the SPI bus driver rather than the nrf24l01p driver. See also: - RIOT-OS#1704 - RIOT-OS#2315 Signed-off-by: Joakim Gebart <[email protected]>
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The baudrate control for the SPIs are currently not set correctly during initialization. The SPIs on the stm32f4xx series run either on the APB1 or the APB2 bus which are clocked differently (APB1=42MHz, APB2=84MHz). Therefore during spi initialization we need to distinguish between the two possible clock rates to compute our prescaler.
Additionally, the previously configured prescalers were wrong as well and didn't lead to the desired speed on either bus. Please refer to baud rate control bits in the control register at page 905 of the reference manual where f_pclk is the clock speed of the used bus.