cpu/esp32: fix compilation for GCC 15.2 on ESP32x RISC-V SoCs#22017
Conversation
RISC-V variants of ESP32x do not have a floating point unit. The use of floating point hardware must therefore be disabled in GCC 15.2 to avoid compilation errors.
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@leandrolanzieri It is a very small fix and I would like to include this PR in version 2026.01 so that we can upgrade GCC in riotdocker and Murdock during the next release cycle. The latter will be necessary for future updates of the ESP-IDF SDK. If it is OK for you, I would create a backport PR once this PR is merged. |
I think I don't fully understand, why is this needed in the release in order to bump the toolchain on the next release? |
When using |
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Ok, we can do it. Just this morning I created RC2, but I guess we can have an RC3 without affecting the schedule much. |
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@gschorcht you can create the backport |
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@leandrolanzieri Thanks for reviewing and merging. |
Contribution description
This PR fixes the compilation of the QCBOR package for RISC-V variants of ESP32x SoCs with GCC 15.2.
RISC-V variants of ESP32x do not have a floating point unit. The use of floating point hardware must be explicitly disabled in GCC 15.2 to avoid compilation errors.
The change also works with the current toolchain, which uses GCC 14.2. However, it is necessary in order to be able to switch the GCC version in riotdocker and Murdock first before the ESP-IDF can be ugraded which requires GCC 15.2.
Testing procedure
Compile and flash
tests/pkg/qcborfor any ESP32x RISC-V board, for example:Without the PR, the compilation fails. With the PR, the compilation and the test work:
Issues/PRs references