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RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller#21753

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Teufelchen1 merged 19 commits intoRIOT-OS:masterfrom
AnnsAnns:rp2350_common_the_third_and_final
Feb 24, 2026
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RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller#21753
Teufelchen1 merged 19 commits intoRIOT-OS:masterfrom
AnnsAnns:rp2350_common_the_third_and_final

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@AnnsAnns AnnsAnns commented Sep 30, 2025

Contribution description

After two failed attempts, I finally managed to get a shared and unified setup working for the RP2350. As opposed to the other approaches I took, where I tried to fully unify both the RISCV and ARM versions, this version takes a different approach similar to cortexm_common or riscv_common where each CPU still exists as a separate entity, e.g. rp2350_arm and rp2350_riscv but uses the shared rp2350_common folder.

This PR supersedes both #21745 and #21746, as in it:

  • adds support for the Hazard3 CPU used on the RP2350
  • adds support for the XH3IRQ Interrupt Controller used by the Hazard3. While fairly similar to CLIC/PLIC, the Hazard3 on the RP2350 actually has a custom interrupt controller to "mimick" the way interrupts work on the Cortex ARM side, even having support for direct vector table jumps (Not enabled here since I wanted to still use the trap_entry/trap_handler of riscv_common.
  • updates the uart
  • enables interrupts on the CortexM33
  • unifies both the RISCV and ARM side of the RP2350
  • renames rp2350 (arm version) to rp2350_arm
  • renames rpi-pico-2 (arm version) to rpi-pico-2-arm
  • fixes debugging completely (GDB now runs smoothly both on ARM and RISCV)

However, as of now, it does not yet add the multicore example. All the points raised in the other PRs also still hold true.

Testing procedure

Remember to specify USEMODULE += stdio_uart if you wish to print via UART.

For my testing I mostly modified examples/basic/blinky to also print. On RISCV you can also use xh3irq_force_irq to force interrupts for testing purposes, for example, on each blinky loop, if you feel like it :)

RISCV

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-riscv flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-riscv flash to flash it using picotool.

ARM

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-arm flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-arm flash to flash it using picotool.

Issues/PRs references

@github-actions github-actions bot added Area: doc Area: Documentation Area: build system Area: Build system Area: boards Area: Board ports Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Sep 30, 2025
@crasbe crasbe added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Sep 30, 2025
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crasbe commented Sep 30, 2025

Would you mind creating a "DELETEME" commit that adds the two boards to the .murdock file, so that the CI tests actually are meaningful? :)

@AnnsAnns AnnsAnns requested a review from kaspar030 as a code owner September 30, 2025 14:30
@github-actions github-actions bot added the Area: CI Area: Continuous Integration of RIOT components label Sep 30, 2025
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riot-ci commented Sep 30, 2025

Murdock results

✔️ PASSED

8ff7adb cpu/rp2350_common: reduce stack size to main stack default

Success Failures Total Runtime
11001 0 11004 08m:33s

Artifacts

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@mguetschow mguetschow left a comment

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Great work! 🎉 Some comments from briefly skimming over the changes.

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Thank you for all the reviews (esp. so quickly 🐎), I will try to go through all the points mentioned and fix them 🐸 👉👉

@crasbe crasbe added the CI: no fast fail don't abort PR build after first error label Oct 1, 2025
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AnnsAnns commented Oct 1, 2025

Moving the register addresses out of the assembly caused the assembler to complain. Since that is the only location they are used I moved them back into the function and simply explained them within the function.

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crasbe commented Oct 2, 2025

I resolved some of the review comments that were fixed, but here are the ones that either haven't been addressed yet or where I'm not sure if they should be marked as resolved yet.

#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)

@AnnsAnns AnnsAnns force-pushed the rp2350_common_the_third_and_final branch 2 times, most recently from 2c0dbf3 to 8ff7adb Compare February 24, 2026 18:13
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Weak approve since I have only skimmed over it right now.

Thanks for doing this!

@Teufelchen1 Teufelchen1 added this pull request to the merge queue Feb 24, 2026
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YOLO

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AnnsAnns commented Feb 24, 2026

Responsibility for this merge is now 100% with @Teufelchen1, I take 0% blame :)

Merged via the queue into RIOT-OS:master with commit f665d06 Feb 24, 2026
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crasbe commented Feb 24, 2026

Congratulations 🥳

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Thank you so much for all the reviews & reviewers over the last months 🫡

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Area: boards Area: Board ports Area: build system Area: Build system Area: cpu Area: CPU/MCU ports Area: doc Area: Documentation Area: Kconfig Area: Kconfig integration Area: pkg Area: External package ports CI: no fast fail don't abort PR build after first error CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms Type: new feature The issue requests / The PR implemements a new feature for RIOT

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5 participants