boards: Bitcraze Crazyflie 2.1 main application board support#21689
boards: Bitcraze Crazyflie 2.1 main application board support#21689crasbe merged 1 commit intoRIOT-OS:masterfrom
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That depends. Is is likely that RIOT would run on the radio MCU as well, or is that always considered "static" like an on-board programmer on ST's Nucleo devboards? |
crasbe
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Thank you for your new board addition, RIOT on a drone might be a first :D
There are some minor things from my side apart of the comments below:
- There are some static errors (such as
too many consecutive empty lines) that need to be addressed. - The board name should follow our naming convention: https://github.com/RIOT-OS/RIOT/blob/master/doc/memos/rdm0003.md
A possible name would bebitcraze-crazyflie. However considering there are multiple revisions of the Crazyflie (which might be incompatible?), it might make sense to name itbitcraze-crazyflie21or similar.
boards/crazyflie/Kconfig
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| # Copyright (c) 2025 LeonardHerbst | ||
| # | ||
| # This file is subject to the terms and conditions of the GNU Lesser | ||
| # General Public License v2.1. See the file LICENSE in the top level | ||
| # directory for more details. |
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The copyright notices should be migrated to the new SPDX format, as described in #21515
boards/crazyflie/doc.md
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| It has two oboard microcontrollers, a nRF51822 used for radio communication and power management and | ||
| a STM32F405 (this board) used for running the main application. |
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| It has two oboard microcontrollers, a nRF51822 used for radio communication and power management and | |
| a STM32F405 (this board) used for running the main application. | |
| It has two onboard microcontrollers, an nRF51822 used for radio communication and power management and | |
| an STM32F405 (this board definition) used for running the main application. |
boards/crazyflie/doc.md
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| | Package | LQFP64 | | ||
| | RAM | 192 KiB (128 KiB RAM + 64 KiB CCMRAM) | | ||
| | Flash | 1024 KiB | | ||
| | Frequency | up to 168 MHz | |
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It would be good to specify at which clock rate the MCU is clocked when using RIOT.
boards/crazyflie/doc.md
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| ### Flash the board | ||
| Prerequisites: | ||
| - the crazyflie NRF firmware runs on the NRF [instructions](https://www.bitcraze.io/documentation/repository/crazyflie2-nrf-firmware/master/build/build/) |
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| - the crazyflie NRF firmware runs on the NRF [instructions](https://www.bitcraze.io/documentation/repository/crazyflie2-nrf-firmware/master/build/build/) | |
| - the Crazyflie NRF firmware runs on the NRF [instructions](https://www.bitcraze.io/documentation/repository/crazyflie2-nrf-firmware/master/build/build/) |
Likewise for other occurances in the document.
It appears that bitcraze should be written in lowercase and Crazyflie with a capital C.
boards/crazyflie/include/board.h
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| * @file | ||
| * @brief Board specific definitions for the Crazyflie 2.1 | ||
| * | ||
| * @author LeonardHerbst <[email protected]> |
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| * @author LeonardHerbst <leonard.herbst@tu-dresden.de> | |
| * @author Leonard Herbst <leonard.herbst@tu-dresden.de> |
The same is true for the other files.
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| /* This board provides an HSE */ | ||
| #ifndef CONFIG_BOARD_HAS_HSE | ||
| #define CONFIG_BOARD_HAS_HSE 1 |
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| #define CONFIG_BOARD_HAS_HSE 1 | |
| # define CONFIG_BOARD_HAS_HSE 1 |
Thanks for the quick response! |
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Either |
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Regarding the CI error, I think you will have to extend the STM32 clock configuration, as there seem to be no provisions for the STM32F405 yet (there is no other board that supports it yet): https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/stmclk/stmclk_f2f4f7.c |
crasbe
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There are some static errors, please fix them too.
You can also run make static-test locally in the base directory before pushing.
| # Copyright (c) 2025 TU Dresden | ||
| # | ||
| # This file is subject to the terms and conditions of the GNU Lesser | ||
| # General Public License v2.1. See the file LICENSE in the top level | ||
| # directory for more details. |
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| # Copyright (c) 2025 TU Dresden | |
| # | |
| # This file is subject to the terms and conditions of the GNU Lesser | |
| # General Public License v2.1. See the file LICENSE in the top level | |
| # directory for more details. | |
| # SPDX-FileCopyrightText: 2025 TU Dresden | |
| # SPDX-License-Identifier: LGPL-2.1-only |
This file too.
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| /* This board provides an LSE */ | ||
| #ifndef CONFIG_BOARD_HAS_LSE | ||
| # define CONFIG_BOARD_HAS_LSE 1 |
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RIOT does not use horizontal tabs, only spaces.
| #ifndef CONFIG_BOARD_HAS_LSE | ||
| # define CONFIG_BOARD_HAS_LSE 1 | ||
| #endif | ||
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| /* This board provides an HSE */ | ||
| #ifndef CONFIG_BOARD_HAS_HSE | ||
| # define CONFIG_BOARD_HAS_HSE 1 | ||
| #endif | ||
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| /* The HSE provides a 8MHz clock */ | ||
| #ifndef CONFIG_CLOCK_HSE | ||
| # define CONFIG_CLOCK_HSE MHZ(8) | ||
| #endif |
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| #ifndef CONFIG_BOARD_HAS_LSE | |
| # define CONFIG_BOARD_HAS_LSE 1 | |
| #endif | |
| /* This board provides an HSE */ | |
| #ifndef CONFIG_BOARD_HAS_HSE | |
| # define CONFIG_BOARD_HAS_HSE 1 | |
| #endif | |
| /* The HSE provides a 8MHz clock */ | |
| #ifndef CONFIG_CLOCK_HSE | |
| # define CONFIG_CLOCK_HSE MHZ(8) | |
| #endif | |
| #ifndef CONFIG_BOARD_HAS_LSE | |
| # define CONFIG_BOARD_HAS_LSE 1 | |
| #endif | |
| /* This board provides an HSE */ | |
| #ifndef CONFIG_BOARD_HAS_HSE | |
| # define CONFIG_BOARD_HAS_HSE 1 | |
| #endif | |
| /* The HSE provides a 8MHz clock */ | |
| #ifndef CONFIG_CLOCK_HSE | |
| # define CONFIG_CLOCK_HSE MHZ(8) | |
| #endif |
The indentation level for preprocessor commands is only two spaces.
| warning: Member motor_driver_config\[\] \(variable\) of | ||
| warning: Member MOTOR_DRIVER_NUMOF \(macro definition\) of |
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Please provide documentation for the variables instead of adding another exception to the already-too-long list of exceptions.
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You'll have to add the board to the BLACKLIST of shame of the RIOT/tests/sys/usbus_cdc_ecm/Makefile Lines 11 to 22 in 703feab The STM32F405 only has four endpoints, which is not enough to use USB CDC ECM and USB CDC ACM at the same time. |
crasbe
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Please squash your commits.
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Contribution description
Support for the Crazyflie 2.1 main application MCU. The Crazyflie 2.1 uses a dual-MCU setup. One for the main application and one for radio and power management.
I was usure wheather I should include the cpu family in the board name.
Testing procedure
I tested the timers, dma, uart, SPI, I2C and running the motors.
I did not test the adc unit.