cpu/samd5x: improve can-initialization#21173
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kfessel merged 1 commit intoRIOT-OS:masterfrom Apr 5, 2025
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I don't have a device to test this, but looks sensible from a quick glance. Do you have a pointer to the datasheet?
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| /* setup */ | ||
| pchctrl = GCLK_PCHCTRL_GEN(dev->conf->gclk_src); | ||
| GCLK->PCHCTRL[pchid].reg = pchctrl; |
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why no busy wait loop here?
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at this point the register is changeable (since the channel is deactivated)
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I think @mguetschow suggested to add a comment here to explain why not waiting here, in contrast to the other writes.
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I tested this with my SAME54-XPRO. In master: TX works, RX does not, unless But having the clock init better matching the process in the datasheet does have merit. Please squash! |
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Contribution description
This makes the can initialization for the samd5x more stable
Testing procedure
find a Board that uses this cpu but has sight problems of getting the can bus up reliably
find its more reliable with this Patch
Issues/PRs references
SAM D5x/E5x Family datasheet page 144 (DS60001507M) 14.6.3.3