boards/samd5x: GCLK source for ADC must not exceed 100 MHz#20932
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benpicco merged 1 commit intoRIOT-OS:masterfrom Oct 22, 2024
Merged
boards/samd5x: GCLK source for ADC must not exceed 100 MHz#20932benpicco merged 1 commit intoRIOT-OS:masterfrom
benpicco merged 1 commit intoRIOT-OS:masterfrom
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dylad
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LGTM.
doccheck is complaining. Feels free to squash right away.
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Contribution description
When not otherwise specified, the ADC will be clocked by GCLK_MAIN which in case of SAM D5x/E5x is configured to run at 120 MHz.
This exceeds the maximum allowed input GCLK frequency.
We could use
DIV4here as well, but as long as we don't have the sample length calculation in, better run the ADC at a more conservative pace.Testing procedure
tests/periph/adcstill worksIssues/PRs references