cpu/stm32: add support for STM32C0 and NUCLEO-C031C6 #20300
cpu/stm32: add support for STM32C0 and NUCLEO-C031C6 #20300benpicco merged 3 commits intoRIOT-OS:masterfrom
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Code looks good to me!
Nice addition.
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One more thing: Since the STM32C031C6 has very little memory (32k ROM, 12k RAM) I expect that some applications won't fit on it. CI tries to build every application for every board, so you need to tell it which ones to exclude for a board because they won't fit. You can do this by running This will build all applications & tests for You then need to commit the updated |
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Looks like there is no low power timer on STM32C0 - so you might have to remove the |
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There is not a dedicated low-power timer |
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The only requirement for |
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Alright. I'll do that. I still get build errors for |
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I think the failures of
LVGL still fails though. I also get a brief message on spi_dma before it's |
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That's because you don't advertise the |
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I've restored and re-built the |
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looks like (at least) |
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That's just a sporadic failure that occurs when CI is under high load. |
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That was a great first PR! |
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Thanks for your help. I'll get back to GD32 it but it might be a few weeks, yet. |
Cleaned-up commit history of PR #20267
Support added for ST Micro's board
NUCLEO-C031C6, it's cpuSTM32C031C6, and the rest of the cpu familySTM32C0XX(asCPU_FAM_STM32C0). This currently includesSTM32C011andSTM32C031, but code for identification has also been added for theSTM32C071andSTM32C091lines due out later this year.Code was adapted from
CPU_FAM_STM32G0where applicable.The most important difference in the STM32C0 product line is the removal of the PLL. As coded the default clock source is HSI.
fixes #19210