cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2#19962
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bors[bot] merged 1 commit intoRIOT-OS:masterfrom Oct 2, 2023
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cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2#19962bors[bot] merged 1 commit intoRIOT-OS:masterfrom
bors[bot] merged 1 commit intoRIOT-OS:masterfrom
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maribu
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Contribution description
This PR fixes the RISC-V ISA spec in compiler and linker flags for ESP32-C3 and GCC 12.2.
Earlier versions of the specs and tools subsumed
zicsrandzifenceiinto theIextension which is no longer the case. Therefore, the RISC-V ISA spec in compiler and linker flags had to be changed from-march=rv32imcto-march=rv32imc_zicsr_zifencei.As a consequence floating-point arithmetics and I/O were no longer working with
-march=rv32imcwith GCC 12.2 sinceriscv32-esp-elf/lib/libm_nano.awas linked instead ofriscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libm_nano.abecauseriscv32-esp-elf/lib/rv32imc/ilp32/libm_nano.ais not existing in the toolchain.Testing procedure
Add a
in the
mainfunction of any application. Without this PR the application should crash while it should work with this PR.Issues/PRs references