cpu/stm32/periph_adc: fixes and improvements for L4 support by gschorcht · Pull Request #19571 · RIOT-OS/RIOT

gschorcht · 2023-05-10T10:43:37Z

Contribution description

This PR provides the following fixes and improvements for the periph_adc implementation for STM32L4.

Support STM32L496AG added.
Instead of defining the number of ADC devices for each MCU model, the number of ADC devices is determined from ADCx definitions in CMSIS header.
MCU specific register/value defines are valid for all L4 MCUs, model based conditional compilation is removed.
The ADC clock disable function is fixed using a counter. The counter is incremented in prep and decremented in done. The ADC clock is disabled if the counter becomes 0.
For boards that have not connected the V_REF+ pin to an external reference voltage, the VREFBUF peripheral can be used as V_REF+ (if supported) by setting VREFBUF_ENABLE=1.
The ASCR register is available and has to be set for all STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx MCUs. Instead of using the CPU model for conditional compilation, the CPU line is used to support all MCU of that lines.
Setting of SQR1 is fixed. Setting the SQR1 did only work before because the ADC_SRQ_L is set to 0 for a sequence length of 1.
Setting the ADC_CCR_CKMODE did only work for the reset state. It is now cleared before it is set. Instead of using the ADC_CCR_CKMODE_x bits to set the mode, the mode defines are used.
Support for V_REFINT as ADC channel added.

Testing procedure

Issues/PRs references

Instead of defining the number of ADC devices for each MCU model, the number of ADC devices is determined from ADCx definitions in CMSIS header.

The ADC clock disable is fixed using a counter. The counter is incremented in `prep` and decremented in `done`. The ADC clock is disabled if the counter becomes 0.

For boards that have not connected the V_REF+ pin to an external reference voltage, the VREFBUF peripheral can be used as V_REF+ if supported by setting `VREFBUF_ENABLE=1`.

The ASCR register is available and has to be set for all STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx MCUs. Instead of using the CPU model for conditional compilation, the CPU line is used to support all MCU of that lines.

The setting of SQR1 is fixed. Setting the SQR1 did only work before because the ADC_SRQ_L is set to 0 for a sequence length of 1.

riot-ci · 2023-05-10T10:52:43Z

Murdock results

✔️ PASSED

caa50a5 cpu/stm32/periph_adc: support V_REFINT as ADC channel on L4

Success	Failures	Total	Runtime
6931	0	6931	08m:50s

Artifacts

Documentation preview

benpicco · 2023-05-15T11:43:51Z

bors merge

18056: pkg/cmsis: use unique package for CMSIS headers, DSP and NN modules r=benpicco a=aabadie 19571: cpu/stm32/periph_adc: fixes and improvements for L4 support r=benpicco a=gschorcht ### Contribution description This PR provides the following fixes and improvements for the `periph_adc` implementation for STM32L4. - Support STM32L496AG added. - Instead of defining the number of ADC devices for each MCU model, the number of ADC devices is determined from ADCx definitions in CMSIS header. - MCU specific register/value defines are valid for all L4 MCUs, model based conditional compilation is removed. - The ADC clock disable function is fixed using a counter. The counter is incremented in `prep` and decremented in `done`. The ADC clock is disabled if the counter becomes 0. - For boards that have not connected the V_REF+ pin to an external reference voltage, the VREFBUF peripheral can be used as V_REF+ (if supported) by setting `VREFBUF_ENABLE=1`. - The ASCR register is available and has to be set for all STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx MCUs. Instead of using the CPU model for conditional compilation, the CPU line is used to support all MCU of that lines. - Setting of SQR1 is fixed. Setting the SQR1 did only work before because the `ADC_SRQ_L` is set to 0 for a sequence length of 1. - Setting the `ADC_CCR_CKMODE` did only work for the reset state. It is now cleared before it is set. Instead of using the `ADC_CCR_CKMODE_x` bits to set the mode, the mode defines are used. - Support for V_REFINT as ADC channel added. ### Testing procedure 19589: gnrc/gnrc_netif_hdr_print: printout timestamp if enabled r=benpicco a=chudov Co-authored-by: Alexandre Abadie <[email protected]> Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: chudov <[email protected]>

bors · 2023-05-15T12:09:16Z

Build failed (retrying...):

Murdock

Setting the `ADC_CCR_CKMODE` did only work for the reset state. It is now cleared before it is set. Instead of using the `ADC_CCR_CKMODE_x` bits to set the mode, the mode defines are used.

bors · 2023-05-15T12:25:28Z

Canceled.

gschorcht · 2023-05-15T12:25:57Z

Small typo 😎 Fixed.

gschorcht · 2023-05-15T12:35:28Z

I squashed the small fix directly

adc_l4.c:153:21: error: 'ADC_CCR_CKMODE_HCLK_22' undeclared (first use in this function); did you mean 'ADC_CCR_CKMODE_HCLK_2'?
  153 |         ADC->CCR |= ADC_CCR_CKMODE_HCLK_22 << ADC_CCR_CKMODE_Pos;
      |                     ^~~~~~~~~~~~~~~~~~~~~~
      |                     ADC_CCR_CKMODE_HCLK_2```

benpicco · 2023-05-15T12:39:39Z

bors merge

bors · 2023-05-15T15:35:01Z

Build succeeded!

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gschorcht · 2023-05-16T04:40:18Z

Thanks

18005: pkg/semtech-loramac: model in Kconfig r=aabadie a=aabadie 19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ 19650: drivers/nrf24l01p: model in kconfig r=aabadie a=aabadie 19660: cpu/rpx0xx: Fix kconfig model r=aabadie a=MrKevinWeiss ### Contribution description Broken master due to incorrect model of the periph_pio in kconfig. ### Testing procedure Green murdock (now that the board is added to the list) ### Issues/PRs references Look at the master CI... Co-authored-by: Alexandre Abadie <[email protected]> Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: MrKevinWeiss <[email protected]>

19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ 19650: drivers/nrf24l01p: model in kconfig r=aabadie a=aabadie 19660: cpu/rpx0xx: Fix kconfig model r=aabadie a=MrKevinWeiss ### Contribution description Broken master due to incorrect model of the periph_pio in kconfig. ### Testing procedure Green murdock (now that the board is added to the list) ### Issues/PRs references Look at the master CI... Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: Alexandre Abadie <[email protected]> Co-authored-by: MrKevinWeiss <[email protected]>

19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ Co-authored-by: Gunar Schorcht <[email protected]>

gschorcht added 7 commits May 10, 2023 12:19

cpu/stm32/periph_adc: support STM32L496AG

c107302

cpu/stm32/periph_adc: determine number of ADC from CMSIS header

e4ca7b8

Instead of defining the number of ADC devices for each MCU model, the number of ADC devices is determined from ADCx definitions in CMSIS header.

cpu/stm32/periph_adc: defines are valid for all L4 MCUs

c4d0908

cpu/stm32/periph_adc: fix ADC clock disable for L4

d8bd2d9

The ADC clock disable is fixed using a counter. The counter is incremented in `prep` and decremented in `done`. The ADC clock is disabled if the counter becomes 0.

cpu/stm32/periph_adc: support for internal V_REF+

ccba70f

For boards that have not connected the V_REF+ pin to an external reference voltage, the VREFBUF peripheral can be used as V_REF+ if supported by setting `VREFBUF_ENABLE=1`.

cpu/stm32/periph_adc: fix SQR1 setting for L4

af8a87a

The setting of SQR1 is fixed. Setting the SQR1 did only work before because the ADC_SRQ_L is set to 0 for a sequence length of 1.

gschorcht requested review from DipSwitch, aabadie, fjmolinas and vincent-d as code owners May 10, 2023 10:43

github-actions bot added Area: cpu Area: CPU/MCU ports Platform: ARM Platform: This PR/issue effects ARM-based platforms labels May 10, 2023

gschorcht mentioned this pull request May 10, 2023

boards: add stm32l496g-disco support #19576

Merged

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benpicco approved these changes May 11, 2023

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gschorcht added 2 commits May 15, 2023 14:24

cpu/stm32/periph_adc: fix CKMODE setting for L4

6247b2a

Setting the `ADC_CCR_CKMODE` did only work for the reset state. It is now cleared before it is set. Instead of using the `ADC_CCR_CKMODE_x` bits to set the mode, the mode defines are used.

cpu/stm32/periph_adc: support V_REFINT as ADC channel on L4

caa50a5

gschorcht force-pushed the cpu/stm32/periph/adc_l4_fixes_improvements branch from 8fee2a3 to caa50a5 Compare May 15, 2023 12:25

bors bot merged commit 2b97b76 into RIOT-OS:master May 15, 2023

gschorcht deleted the cpu/stm32/periph/adc_l4_fixes_improvements branch May 22, 2023 14:58

benpicco added this to the Release 2023.07 milestone Aug 2, 2023

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cpu/stm32/periph_adc: fixes and improvements for L4 support#19571

cpu/stm32/periph_adc: fixes and improvements for L4 support#19571
bors[bot] merged 9 commits intoRIOT-OS:masterfrom
gschorcht:cpu/stm32/periph/adc_l4_fixes_improvements

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gschorcht commented May 10, 2023

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