cpu/gd32v: add riotboot support by gschorcht · Pull Request #19411 · RIOT-OS/RIOT

gschorcht · 2023-03-19T23:30:31Z

Contribution description

This PR provides riotboot support for GD32V.

Testing procedure

Use any GD32V board with a JTAG adapter and flash the bootloader:

PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C bootloaders/riotboot flash

Flash slot 0 and set RIOT_VERSION to 1

USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=1 \
PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot0
...
### Flashing Target ###
Binfile detected, adding ROM base address: 0x08000000
Flashing with IMAGE_OFFSET: 0x08001000

> main(): This is RIOT! (Version: 1)
test_shell.

Flash slot 1 and set RIOT_VERSION to 2

USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=2 \
PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot1
...
### Flashing Target ###
Binfile detected, adding ROM base address: 0x08000000
Flashing with IMAGE_OFFSET: 0x08010800

> main(): This is RIOT! (Version: 2)
test_shell.

Issues/PRs references

riot-ci · 2023-03-19T23:44:17Z

Murdock results

✔️ PASSED

373b10e tests/riotboot_flashwrite: blacklist GD32V boards

Success	Failures	Total	Runtime
6882	0	6882	08m:51s

Artifacts

Documentation preview

cpu/gd32v/Makefile.include

gschorcht · 2023-03-20T11:12:11Z

I had to push further commits that improve/fix gd32vf103_clock_init. This fix is required for riotboot if the application uses the USB peripheral. In this case, the core clock has to be changed from 108 MHz (riotboot) to 96 MHz (application).

gschorcht · 2023-03-20T12:47:06Z

Commit 53db2ba changes SLOT1_OFFSET to hex format because for better readability and compatibility with other address and offset numbers.

-DSLOT0_LEN=0xe000 -DSLOT0_OFFSET=0x4000 -DSLOT1_LEN=0xe000 -DSLOT1_OFFSET=73728

vs

-DSLOT0_LEN=0xe000 -DSLOT0_OFFSET=0x4000 -DSLOT1_LEN=0xe000 -DSLOT1_OFFSET=0x12000

benpicco · 2023-04-12T13:21:42Z

bors merge

19411: cpu/gd32v: add riotboot support r=benpicco a=gschorcht ### Contribution description This PR provides `riotboot` support for GD32V. ### Testing procedure Use any GD32V board with a JTAG adapter and flash the bootloader: ```python PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C bootloaders/riotboot flash ``` Flash slot 0 and set `RIOT_VERSION` to 1 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=1 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot0 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08001000 ``` ```python > main(): This is RIOT! (Version: 1) test_shell. ``` Flash slot 1 and set `RIOT_VERSION` to 2 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=2 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot1 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08010800 ``` ```python > main(): This is RIOT! (Version: 2) test_shell. ``` ### Issues/PRs references 19432: boards/esp32: deduplication in common ESP32x board definitions r=benpicco a=gschorcht ### Contribution description The PR reduced code duplication in `boards/common/esp32*`. The PR moves the header files from `boards/common/esp32s3/include` that can be used for all types of ESP32x SoCs to a new common ESP32x board definition which is then included by all common ESP32x board definitions. ### Testing procedure Green CI. ### Issues/PRs references 19461: drivers/enc28j60: fix ISR routine and bth r=benpicco a=peteut Co-authored-by: Gunar Schorcht <[email protected]> Co-authored-by: Alain Péteut <[email protected]>

bors · 2023-04-12T13:49:06Z

Build failed (retrying...):

Murdock

19411: cpu/gd32v: add riotboot support r=benpicco a=gschorcht ### Contribution description This PR provides `riotboot` support for GD32V. ### Testing procedure Use any GD32V board with a JTAG adapter and flash the bootloader: ```python PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C bootloaders/riotboot flash ``` Flash slot 0 and set `RIOT_VERSION` to 1 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=1 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot0 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08001000 ``` ```python > main(): This is RIOT! (Version: 1) test_shell. ``` Flash slot 1 and set `RIOT_VERSION` to 2 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=2 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot1 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08010800 ``` ```python > main(): This is RIOT! (Version: 2) test_shell. ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

gschorcht · 2023-04-12T13:58:41Z

Ah, riotboot_serial requires also commit a3b3ec9 from my riotboot-dfu branch.

bors · 2023-04-12T14:05:58Z

Build failed:

Murdock

benpicco · 2023-04-16T21:34:52Z

bors merge

19411: cpu/gd32v: add riotboot support r=benpicco a=gschorcht ### Contribution description This PR provides `riotboot` support for GD32V. ### Testing procedure Use any GD32V board with a JTAG adapter and flash the bootloader: ```python PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C bootloaders/riotboot flash ``` Flash slot 0 and set `RIOT_VERSION` to 1 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=1 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot0 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08001000 ``` ```python > main(): This is RIOT! (Version: 1) test_shell. ``` Flash slot 1 and set `RIOT_VERSION` to 2 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=2 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot1 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08010800 ``` ```python > main(): This is RIOT! (Version: 2) test_shell. ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-04-16T23:41:46Z

Build failed:

Murdock

`riotboot_slot` uses `ARRAY_SIZE` which is defined in `container.h` but not yet included on some plattforms.

To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.

To be able to reconfigure the PLL multiplier in clock configuration, the existing value has to be reset first. This becomes necessary when changing the core clock, e.g. when booting with riotboot an application that uses USB.

Using hex number for addresses and address offsets improves the readability.

Some platforms such as RISC-V don't support numbers given with unit (32K)

benpicco · 2023-04-18T08:58:38Z

bors merge

19411: cpu/gd32v: add riotboot support r=benpicco a=gschorcht ### Contribution description This PR provides `riotboot` support for GD32V. ### Testing procedure Use any GD32V board with a JTAG adapter and flash the bootloader: ```python PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C bootloaders/riotboot flash ``` Flash slot 0 and set `RIOT_VERSION` to 1 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=1 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot0 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08001000 ``` ```python > main(): This is RIOT! (Version: 1) test_shell. ``` Flash slot 1 and set `RIOT_VERSION` to 2 ```python USEMODULE=stdio_uart FEATURES_REQUIRED=riotboot RIOT_VERSION=2 \ PROGRAMMER=openocd BOARD=sipeed-longan-nano make -C tests/shell riotboot/flash-slot1 ... ### Flashing Target ### Binfile detected, adding ROM base address: 0x08000000 Flashing with IMAGE_OFFSET: 0x08010800 ``` ```python > main(): This is RIOT! (Version: 2) test_shell. ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-04-18T13:14:45Z

Build failed:

Murdock

gschorcht · 2023-04-19T10:56:21Z

I had to blacklist GD32V boards. I hope that CI is now happy.

benpicco · 2023-04-19T12:55:09Z

The board has 128k Flash, why does riotboot_flashwrite overflow it by 10k?
Almost feels like something got messed up with the linker script.

nvm those tests all use two slots which leave less than 64k for the app

benpicco · 2023-04-19T12:57:47Z

bors merge

bors · 2023-04-19T15:00:02Z

Build succeeded:

gschorcht · 2023-04-19T17:27:53Z

Thanks.

gschorcht requested review from aabadie, bergzand, fjmolinas and kaspar030 as code owners March 19, 2023 23:30

github-actions bot added Area: boards Area: Board ports Area: cpu Area: CPU/MCU ports Area: sys Area: System Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms labels Mar 19, 2023

gschorcht added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Mar 19, 2023

benpicco reviewed Mar 19, 2023

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cpu/gd32v/Makefile.include Outdated Show resolved Hide resolved

gschorcht force-pushed the cpu/gd32v/riotboot branch from d1cb149 to a1b75ae Compare March 20, 2023 11:32

github-actions bot added the Platform: ARM Platform: This PR/issue effects ARM-based platforms label Mar 20, 2023

gschorcht mentioned this pull request Mar 20, 2023

drivers/mtd_flashpage: allow to define AUX slot on flash #18608

Merged

benpicco approved these changes Mar 31, 2023

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gschorcht added CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR and removed CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Apr 12, 2023

github-actions bot added the Area: examples Area: Example Applications label Apr 17, 2023

gschorcht requested a review from MrKevinWeiss as a code owner April 18, 2023 04:16

github-actions bot added the Area: Kconfig Area: Kconfig integration label Apr 18, 2023

gschorcht added 12 commits April 18, 2023 06:20

sys/riotboot: fix compilation error of riotboot_slot

f4f716a

`riotboot_slot` uses `ARRAY_SIZE` which is defined in `container.h` but not yet included on some plattforms.

cpu/riscv_common: rename cpu.h to cpu_common.h

2ae7566

To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.

cpu/riscv_common: add riotboot linker support

1ad397f

cpu/gd32v: add riotboot support

f6cb8b9

boards/common/gd32v: enable riotboot feature

92e0f25

cpu/gd32c: cleanup in clock configuration

dc45b7b

cpu/gd32v: allow reconfig PLL multiplier in clock config

9be2421

To be able to reconfigure the PLL multiplier in clock configuration, the existing value has to be reset first. This becomes necessary when changing the core clock, e.g. when booting with riotboot an application that uses USB.

sys/riotboot: common default NUM_SLOT, SLOT_* config

06426c4

sys/riotboot: uses SLOT1_OFFSET in hex format

2e32d4e

Using hex number for addresses and address offsets improves the readability.

sys: define CPU_RAM_SIZE as hex number

3b2da3e

Some platforms such as RISC-V don't support numbers given with unit (32K)

examples/suit_update: blacklist GD32V boards

ea61309

boards: enable riotboot feature for GD32V boards in Kconfig

dc29a3e

gschorcht force-pushed the cpu/gd32v/riotboot branch from ecf3bfd to dc29a3e Compare April 18, 2023 04:21

tests/riotboot_flashwrite: blacklist GD32V boards

373b10e

gschorcht requested review from MichelRottleuthner and smlng as code owners April 19, 2023 10:54

github-actions bot added the Area: tests Area: tests and testing framework label Apr 19, 2023

bors bot merged commit 88d1d2e into RIOT-OS:master Apr 19, 2023

gschorcht deleted the cpu/gd32v/riotboot branch April 26, 2023 09:25

benpicco added this to the Release 2023.07 milestone Aug 2, 2023

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Testing procedure

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