cpu/esp32: add support for ESP32-C3 SoC family#17844
cpu/esp32: add support for ESP32-C3 SoC family#17844gschorcht wants to merge 83 commits intoRIOT-OS:masterfrom
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Let's hope this PR and the master don't diverge so much until these PRs can be merged. Any required rebase after other changes to |
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| CPU_CORE = xtensa-lx6 | ||
| else ifneq (,$(filter esp32c3,$(CPU_FAM))) | ||
| CPU_ARCH = riscv_esp32 | ||
| CPU_CORE = riscv32 |
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There are allready some riscv32 MCU they use
CPU_CORE := rv32imac (eg.: cpu/gd32v/Makefile.features)
is there a reason to have this riscv32?
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Unfortunately, we can't use cpu/riscv_common as is, please see section "Background" in PR #18260 (comment). In short
- ESP-IDF's
vector.Sandportasm.S, which we use, use a different context frame structure - RISC-V based ESP32x SoCs use a special SoC register
INTERRUPT_CORE0_CPU_INT_THRESH_REGto enable/disable interrupts.
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Ah ok, now I got it. I must have read too superficially. You don't ask why not use cpu/esp_common, but why not use rv32 as CPU_CORE? To be honest, I have to check whether this makes a difference.
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All split-offs are merged now. |
Contribution description
This PR provides the support for the ESP32-C3 SoC family and the ESP32-C3-DevKit board.
For the moment, this PR includes
PR #17601,PR #17841 and PR #17842 to be compilable. Once these PRs are merged this PR is rebased. The first additional commit of this PR is d0210be.Testing procedure
Compilation in CI has to succeed. All peripheral and basis tests have to pass.
Issues/PRs references
Depends on PR #17601Depends on PR #17841
Depends on PR #17842
Prerequisite for PR #18185