cpu/cc26xx_cc13xx: add & link CCFG configuration by jeandudey · Pull Request #14219 · RIOT-OS/RIOT

jeandudey · 2020-06-08T03:44:48Z

Contribution description

The CCFG is the Customer Configuration, this enables us to change it at compile time.

Adds a linker script for cc26x2_cc13x2 processors, describing the memory regions correctly.
- The ROM size was changed from 352K to 360360 bytes (351.9140625K or 0x57FA8) which is the real size.
Adds CCFG vendor code.
Adds FORCE_VDDR_HH configuration option. Enables the usage of +14 dBm PA at the cost of higher current consumption. Disabled by default.

More options when needed (such as the bootloader) can added.

The cc26x2_cc13x2 based boards pass the cortexm_common_ldscript test, should I whitelist them?

Testing procedure

Code should still flash normally without problems.
CFLAGS="-DCONFIG_CC26XX_CC13XX_UPDATE_CCFG=1" make flash BOARD=cc1312-launchpad
Or any other combination using make menuconfig and selecting the option to update the CCFG.

Issues/PRs references

See also #13635

cpu/cc26x2_cc13x2/cpu.c

cpu/cc26x2_cc13x2/ldscripts/cc26x2_cc13x2.ld

cpu/cc26x2_cc13x2/vendor/startup_files/ccfg.c

jeandudey · 2020-06-26T02:16:51Z

I'll see if I can go without vendor code and reuse CCFG code on cc26xx_cc13xx, as it adds too much unnecesary code from the Texas Instruments SDK

jeandudey · 2020-09-23T18:56:07Z

I tried another approach at solving this. Uses Kconfig to let the user select if they want to update the CCFG.

Building with "Update CCFG"

jeandudey@jean ~/D/R/e/hello-world> arm-none-eabi-readelf -S /home/jeandudey/Dev/RIOT/examples/hello-world/bin/cc1312-launchpad/hello-world.elf
There are 23 section headers, starting at offset 0x934c0:

Section Headers:
  [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
  [ 0]                   NULL            00000000 000000 000000 00      0   0  0
  [ 1] .ccfg             PROGBITS        00057fa8 027fa8 000058 00  WA  0   0  4
  [ 2] .text             PROGBITS        00000000 010000 002250 00  AX  0   0 16
  [ 3] .stack            NOBITS          20000000 030000 000200 00  WA  0   0  1
  [ 4] .relocate         REL             20000200 020200 00006c 08  WA  0   0  4
  [ 5] .bss              NOBITS          2000026c 02026c 000700 00  WA  0   0  4
  [ 6] .noinit           PROGBITS        2000096c 028000 000000 00   W  0   0  1
  [ 7] .backup.data      PROGBITS        00000000 028000 000000 00   W  0   0  4
  [ 8] .backup.bss       PROGBITS        00000000 028000 000000 00   W  0   0  4
  [ 9] .debug_info       PROGBITS        00000000 028000 01acb7 00      0   0  1
  [10] .debug_abbrev     PROGBITS        00000000 042cb7 004bfb 00      0   0  1
  [11] .debug_aranges    PROGBITS        00000000 0478b2 0005f0 00      0   0  1
  [12] .debug_ranges     PROGBITS        00000000 047ea2 000a40 00      0   0  1
  [13] .debug_macro      PROGBITS        00000000 0488e2 019aad 00      0   0  1
  [14] .debug_line       PROGBITS        00000000 06238f 00e240 00      0   0  1
  [15] .debug_str        PROGBITS        00000000 0705cf 01c55e 01  MS  0   0  1
  [16] .comment          PROGBITS        00000000 08cb2d 00004c 01  MS  0   0  1
  [17] .ARM.attributes   ARM_ATTRIBUTES  00000000 08cb79 000032 00      0   0  1
  [18] .debug_frame      PROGBITS        00000000 08cbac 0011bc 00      0   0  4
  [19] .debug_loc        PROGBITS        00000000 08dd68 002858 00      0   0  1
  [20] .symtab           SYMTAB          00000000 0905c0 002030 10     21 301  4
  [21] .strtab           STRTAB          00000000 0925f0 000deb 00      0   0  1
  [22] .shstrtab         STRTAB          00000000 0933db 0000e5 00      0   0  1

Without "Update CCFG". Notice that .ccfg section doesn't exist

jeandudey@jean ~/D/R/e/hello-world> arm-none-eabi-readelf -S /home/jeandudey/Dev/RIOT/examples/hello-world/bin/cc1312-launchpad/hello-world.elf
There are 23 section headers, starting at offset 0x934c0:

Section Headers:
  [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
  [ 0]                   NULL            00000000 000000 000000 00      0   0  0
  [ 1] .ccfg             PROGBITS        00057fa8 027fa8 000058 00  WA  0   0  4
  [ 2] .text             PROGBITS        00000000 010000 002250 00  AX  0   0 16
  [ 3] .stack            NOBITS          20000000 030000 000200 00  WA  0   0  1
  [ 4] .relocate         REL             20000200 020200 00006c 08  WA  0   0  4
  [ 5] .bss              NOBITS          2000026c 02026c 000700 00  WA  0   0  4
  [ 6] .noinit           PROGBITS        2000096c 028000 000000 00   W  0   0  1
  [ 7] .backup.data      PROGBITS        00000000 028000 000000 00   W  0   0  4
  [ 8] .backup.bss       PROGBITS        00000000 028000 000000 00   W  0   0  4
  [ 9] .debug_info       PROGBITS        00000000 028000 01acb7 00      0   0  1
  [10] .debug_abbrev     PROGBITS        00000000 042cb7 004bfb 00      0   0  1
  [11] .debug_aranges    PROGBITS        00000000 0478b2 0005f0 00      0   0  1
  [12] .debug_ranges     PROGBITS        00000000 047ea2 000a40 00      0   0  1
  [13] .debug_macro      PROGBITS        00000000 0488e2 019aad 00      0   0  1
  [14] .debug_line       PROGBITS        00000000 06238f 00e240 00      0   0  1
  [15] .debug_str        PROGBITS        00000000 0705cf 01c55e 01  MS  0   0  1
  [16] .comment          PROGBITS        00000000 08cb2d 00004c 01  MS  0   0  1
  [17] .ARM.attributes   ARM_ATTRIBUTES  00000000 08cb79 000032 00      0   0  1
  [18] .debug_frame      PROGBITS        00000000 08cbac 0011bc 00      0   0  4
  [19] .debug_loc        PROGBITS        00000000 08dd68 002858 00      0   0  1
  [20] .symtab           SYMTAB          00000000 0905c0 002030 10     21 301  4
  [21] .strtab           STRTAB          00000000 0925f0 000deb 00      0   0  1
  [22] .shstrtab         STRTAB          00000000 0933db 0000e5 00      0   0  1

The only thing left is testing and review of the code, I'll test for possible errors as I need to be careful with this, as a bad configuration can brick the Launchpads as happened before to me 😓 .

jeandudey · 2020-09-23T22:12:29Z

Update: tested and works like a charm :)

This is the comparision of three hex dumps of the ccfg section, first one with bootloader backdoor enabled (:tada: cc2538-bsl may be useable as a flash option in the near future), second one without anything, the default, and the third with bootloader backdoor + VDDR high which is needed for +14 dBm PA on CC13xx devices.

This also should work on cc26x0 devices, changing the bootloader settings only. If someone has one and could help to test would be appreciated. Works fine on the cc1312-launchpad board which I'm using to test, it succesfully enters the bootloader upon reset by setting the pin level to "active low" and holding the right button (pin number 14).

benpicco

Looks much nicer now!
Now I wonder if this linker magic would also work for sam0 (#14512).

benpicco · 2020-09-23T22:30:24Z

cpu/cc26x0/include/cpu_conf.h

+#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /**< 32 mA */
+#define SET_MODE_CONF_XOSC_FREQ        0x3 /**< 24 MHz xtal */


Should the board config be able to overwrite those?

Not really, AFAIK most of the boards using cc26x0/cc13x0 provide the option to select a 48 MHz crystal, however I haven't seen any out there, and on the guide for crystal selection only makes mention on 24 MHz crystal for cc26x0/cc13x0 CPUs, it's the same for cc26x2/cc13x2 as only 48 MHz crystals are used.

However, should I add a #ifndef guard for future proofing 👀 ?

If other frequencies are possible, we should allow for custom boards to use them.
Adding an #ifndef won’t hurt.

benpicco · 2020-09-23T22:31:18Z

cpu/cc26x2_cc13x2/include/cpu_conf.h

+#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /**< 12 mA */
+#define SET_MODE_CONF_XOSC_FREQ        0x2 /**< 48 MHz xtal */


benpicco · 2020-09-23T22:32:36Z

cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h

+#endif
+
+#ifndef SET_MODE_CONF_VDDS_BOD_LEVEL
+#define SET_MODE_CONF_VDDS_BOD_LEVEL                0x1 /**< 1.8 V or 1.65 V */


Which is which? (0 -> 1.65V, 1 -> 1.8V? Or the other way round?)

cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h

cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld

cpu/cc26x2_cc13x2/Makefile.include

jeandudey · 2020-09-24T15:06:18Z

Comments addressed, added documentation to individual settings. Fixed a bug on cc26x0 which was using the default cortexm.ld link script. Also fixed the ROM size of cc26x0 which is equal to 128K - 88.

.ccfg section on cc2650-launchpad at the correct address

jeandudey@jean ~/D/R/e/hello-world> arm-none-eabi-readelf --hex-dump=.ccfg /home/jeandudey/Dev/RIOT/examples/hello-world/bin/cc2650-launchpad/hello-world.elf

Hex dump of section '.ccfg':
  0x0001ffa8 00008001 00000000 fdff5800 3affaff1 ..........X.:...
  0x0001ffb8 ffffffff ffffffff ffffffff ffffffff ................
  0x0001ffc8 ffffffff ffffffff ffffffff ffffffff ................
  0x0001ffd8 c51fffc5 00000000 00000000 00c5c5ff ................
  0x0001ffe8 00000000 00000000 ffffffff ffffffff ................
  0x0001fff8 ffffffff ffffffff                   ........

cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h

jeandudey · 2020-09-27T22:50:11Z

Comments addressed, fixed a couple nits on cc26x0 such as the ROM length and disabling options on CCFG/Kconfig that aren't available for that family.

This add a custom ldscript for cc26xx_cc13xx CPUs, which allows linking CCFG configuration, usage of GPRAM, etc. Signed-off-by: Jean Pierre Dudey <[email protected]>

This adds almost all registers necessary to flash create the CCFG configuration. Signed-off-by: Jean Pierre Dudey <[email protected]>

> Allows flahsing CCFG configuration using Kconfig, formely "make menuconfig". > Supports cc26x0, cc26x2_cc13x2. > Can be used to enable bootloader backdoor, to use cc2538-bsl flashing script. > Not all options are in Kconfig, most important ones, others can be added in further commits. > On cc13xx targets the VDDR high option can be enabled using Kconfig. > With this, RIOT can flash blank chips and the firmware will run just fine. Signed-off-by: Jean Pierre Dudey <[email protected]>

benpicco

Looks good to me.
Writing the config section is disabled by default, so this should do no harm.

jeandudey requested a review from smlng as a code owner June 8, 2020 03:44

jeandudey mentioned this pull request Jun 8, 2020

[Tracking] cc13x2_cc26x2 drivers support #13635

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jeandudey force-pushed the 2020_06_07-ccfg branch 2 times, most recently from 4a713ff to 752707e Compare June 10, 2020 15:20

benpicco added Area: cpu Area: CPU/MCU ports Type: new feature The issue requests / The PR implemements a new feature for RIOT labels Jun 10, 2020

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jeandudey force-pushed the 2020_06_07-ccfg branch 2 times, most recently from 576a229 to d13bec0 Compare September 23, 2020 18:31

jeandudey requested review from cgundogan, jia200x and leandrolanzieri as code owners September 23, 2020 18:31

jeandudey force-pushed the 2020_06_07-ccfg branch 2 times, most recently from 4cf274a to fb22c6f Compare September 23, 2020 18:45

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jeandudey changed the title ~~cpu/cc26x2_cc13x2: add & link CCFG configuration~~ cpu/cc26xx_cc13xx: add & link CCFG configuration Sep 24, 2020

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jeandudey force-pushed the 2020_06_07-ccfg branch from 718e026 to 72e7936 Compare September 27, 2020 22:46

jeandudey added 3 commits September 27, 2020 17:54

cpu/cc26xx_cc13xx: add custom ld script

d0aedf0

This add a custom ldscript for cc26xx_cc13xx CPUs, which allows linking CCFG configuration, usage of GPRAM, etc. Signed-off-by: Jean Pierre Dudey <[email protected]>

cpu/cc26xx_cc13xx: add CCFG register values

978ea40

This adds almost all registers necessary to flash create the CCFG configuration. Signed-off-by: Jean Pierre Dudey <[email protected]>

jeandudey force-pushed the 2020_06_07-ccfg branch from 72e7936 to 447cdeb Compare September 27, 2020 23:01

benpicco added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Sep 28, 2020

benpicco approved these changes Sep 28, 2020

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benpicco merged commit 615561b into RIOT-OS:master Sep 30, 2020

jeandudey deleted the 2020_06_07-ccfg branch September 30, 2020 13:52

jeandudey mentioned this pull request Sep 30, 2020

cpu/cc26xx_cc13xx: use _rom_length symbol for CCFG origin #15126

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benpicco mentioned this pull request Oct 21, 2020

Particle boards: Support monofirmware builds and uploads #12751

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luisan00 mentioned this pull request Nov 18, 2022

[WIP] cpu/cc26x2_cc13x2: add sub-ghz driver #18737

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		#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /*< 32 mA /
		#define SET_MODE_CONF_XOSC_FREQ 0x3 /*< 24 MHz xtal /

		#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 /*< 12 mA /
		#define SET_MODE_CONF_XOSC_FREQ 0x2 /*< 48 MHz xtal /

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jeandudey commented Jun 8, 2020 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Contribution description

Testing procedure

Issues/PRs references

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