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Citrullin
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benpicco
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Area: cpu
| typedef struct { | ||
| NRF_UARTE_Type *dev; /**< UART with EasyDMA device base register address */ | ||
| NRF_UARTE_Type *dev; /**< UART with EasyDMA device base | ||
| * register address */ |
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No need for that line break.
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Otherwise the line is too long. It was a warning in Travis.
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This looks good, feel free to squash. |
benpicco
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CI: ready for build
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Looks good to me - there should be no potential for regressions.
Looking forward to the PR for the nrf52811mdk.
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Commit message should be somethinkg like |
Citrullin
requested review from
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fjmolinas,
leandrolanzieri and
smlng
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Done |
| isr_spi1_twi1, /* spi1_twi1 */ | ||
| isr_spi0, /* spi 0 */ |
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Hm now I wonder - are you sure those are not just
isr_spi0_twi0, /* spi0_twi0 */
isr_spi1_twi1, /* spi1_twi1 */?
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No, I am not sure. I just copied it from the datasheet. Don't know how it works in detail. But even though, it is wrong. I just looked into it again. It should be spi1_twi0. Just compiled some examples for the nrf52811dk so far. Want to try a SPI example in the near future.
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@benpicco Would be great, if you can tell where these variables are coming from or what happens to them? Where do they get the addresses from?
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This is the interrupt vector table.
When an interrupt occurs the CPU uses the ID of the interrupt source as an index to decide which function to call to handle the interrupt.
So interrupts are enabled for the SPI peripheral, those functions will get called.
They are currently unused, but #14057 will change this.
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@benpicco Yes, I understood this. Thanks for the information that they are not being used. This explains why I couldn't find it :D
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On which page of the data sheet is it?
I couldn't find it yet.
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Ah, tricky
There is a direct relationship between peripheral ID and base address. For example, a peripheral with base
address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a
peripheral with base address 0x4001F000 is assigned ID=31.
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Ah, tricky
There is a direct relationship between peripheral ID and base address. For example, a peripheral with base
address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a
peripheral with base address 0x4001F000 is assigned ID=31.
Yep, exactly the part I messed up. It would make sense to have spi0 and twi0 together, but it isn't ^^
Yes, this is why I thought the order matters. I wasn't sure about the deprecated things so. I kept it like it currently is. But spi should be spim or spis.
This is probably also a bit connected to #10587 then.
| WEAK_DEFAULT void isr_power_clock(void); | ||
| WEAK_DEFAULT void isr_radio(void); | ||
| WEAK_DEFAULT void isr_uart0(void); | ||
| WEAK_DEFAULT void isr_spi0(void); |
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Does this CPU really have a new interrupt?
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See the other isr.
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Is there no |
3 participants
Contribution description
Initial support for the nrf52811 MCU. Will, at some point, add the board configuration for the nrf52811 mdk as well.
Restructuring files etc. makes probably sense at this point.
Testing procedure
Only tested hello world on the nrf52811mdk.
Issues/PRs references
Intitial support the nrf52811 as mentioned in #13054.