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boards/sltb001a: reset before flashing#11548

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cladmi merged 1 commit intoRIOT-OS:masterfrom
cladmi:pr/sltb001a/fix_flashing
May 28, 2019
Merged

boards/sltb001a: reset before flashing#11548
cladmi merged 1 commit intoRIOT-OS:masterfrom
cladmi:pr/sltb001a/fix_flashing

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@cladmi cladmi commented May 20, 2019 •
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When it was running 'hello-world', the board could not be flashed through
JLinkExe anymore and only through the drag and drop support.

By resetting the board before doing 'loadbin' it can now be flashed
properly.

There may be other firmwares too, but hello-world shows enough the issues.

Testing procedure

Try flashing two or more times hello-world

With this pull request it works without issues.

RIOT_CI_BUILD=1 BOARD=sltb001a make --no-print-directory -C examples/hello-world/ flash-only

RIOT_CI_BUILD=1 BOARD=sltb001a make --no-print-directory -C examples/hello-world/ flash-only
/home/harter/work/git/worktree/riot_master/dist/tools/jlink/jlink.sh flash /home/harter/work/git/worktree/riot_master/examples/hello-world/bin/sltb001a/hello-world.bin
### Flashing Target ###
### Flashing at base address 0x0 with offset 0 ###
SEGGER J-Link Commander V6.42d (Compiled Feb 15 2019 13:56:53)
DLL version V6.42d, compiled Feb 15 2019 13:56:43

J-Link Commander will now exit on Error

J-Link Command File read successfully.
Processing script file...

J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: Silicon Labs J-Link OB compiled Nov 28 2017 15:39:56
Hardware version: V1.00
S/N: 440068262
License(s): RDI
VTref=3.308V
Target connection not established yet but required for command.
Device "EFR32MG1PXXXF256" selected.


Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
Cortex-M4 identified.
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.

Downloading file [/home/harter/work/git/worktree/riot_master/examples/hello-world/bin/sltb001a/hello-world.bin]...
Comparing flash   [100%] Done.
Verifying flash   [100%] Done.
J-Link: Flash download: Bank 0 @ 0x00000000: Skipped. Contents already match
O.K.

Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.



Script processing completed.

With master after the second time it fails:

****** Error: Timeout while checking target RAM, RAMCode did not respond in time. (PC = 0x00000009, CPSR = 0x00000008, LR = 0x81000000)!

RIOT_CI_BUILD=1 BOARD=sltb001a make --no-print-directory -C examples/hello-world/ flash-only
/home/harter/work/git/worktree/riot_master/dist/tools/jlink/jlink.sh flash /home/harter/work/git/worktree/riot_master/examples/hello-world/bin/sltb001a/hello-world.bin
### Flashing Target ###
### Flashing at base address 0x0 with offset 0 ###
SEGGER J-Link Commander V6.42d (Compiled Feb 15 2019 13:56:53)
DLL version V6.42d, compiled Feb 15 2019 13:56:43

J-Link Commander will now exit on Error

J-Link Command File read successfully.
Processing script file...

J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: Silicon Labs J-Link OB compiled Nov 28 2017 15:39:56
Hardware version: V1.00
S/N: 440068262
License(s): RDI
VTref=3.307V
Target connection not established yet but required for command.
Device "EFR32MG1PXXXF256" selected.


Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
Cortex-M4 identified.
Halting CPU for downloading file.
Downloading file [/home/harter/work/git/worktree/riot_master/examples/hello-world/bin/sltb001a/hello-world.bin]...

****** Error: Timeout while checking target RAM, RAMCode did not respond in time. (PC = 0x00000009, CPSR = 0x00000008, LR = 0x81000000)!
Failed to prepare for programming.
Failed to execute RAMCode for RAM check!
Unspecified error -1

Script processing completed.

/home/harter/work/git/worktree/riot_master/examples/hello-world/../../Makefile.include:541: recipe for target 'flash-only' failed
make: *** [flash-only] Error 1

Issues/PRs references

Found while running the test suite on the board in #10870

@cladmi
boards/sltb001a: reset before flashing
777592d 
When it was running 'hello-world', the board could not be flashed through
JLinkExe anymore and only through the drag and drop support.

By resetting the board before doing 'loadbin' it can now be flashed
properly.
@cladmi cladmi added Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors) Area: build system Area: Build system Area: tools Area: Supplementary tools Area: boards Area: Board ports labels May 20, 2019
@cladmi cladmi added this to the Release 2019.07 milestone May 20, 2019
@cladmi cladmi requested a review from basilfx May 20, 2019 12:04
@cladmi cladmi mentioned this pull request May 20, 2019
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jcarrano
jcarrano approved these changes May 28, 2019
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Tested. Fixes the issue.

@jcarrano jcarrano added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label May 28, 2019
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cladmi commented May 28, 2019

CI is green. Lets's go.

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cladmi commented May 28, 2019

Thank you for the review.

@cladmi cladmi merged commit fff2718 into RIOT-OS:master May 28, 2019
@cladmi cladmi deleted the pr/sltb001a/fix_flashing branch May 28, 2019 17:40
@cladmi cladmi mentioned this pull request Jul 8, 2019
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@MrKevinWeiss MrKevinWeiss mentioned this pull request Sep 3, 2019
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@basilfx basilfx mentioned this pull request Nov 3, 2020
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Area: boards Area: Board ports Area: build system Area: Build system Area: tools Area: Supplementary tools CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors)

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