@Sizurka found a clever way to automatically generate exti_config from the ASF headers.

I actually used this (with gcc -E) to generate the version used here.

Maybe we can make this common for all sam0 SoCs here too.

@benpicco Nice PR ! I have zero experience with SAM4 but this should not belongs to cpu/sam0
You should rather move it to its own folder and maybe also reuse stuff from cpu/sam_common.

@dylad I think this has more in common with sam0 than with the older sam parts. saml1x doesn't come with a Cortex-M0+ either, it's pretty much just that but with a Cortex-M4F instead of Cortex-M23.

I feel like the thing that separates the sam0 from the sam is that it comes with the SERCOM peripherals - there are differences in other peripherals too that are different between the sam and the sam0 families but similar across sam0 members, but that's the most prominent difference imho.

The two "sam0_common:" commits should preferably have their own PullRequest. No? Even if this PR depends on it.

(( Shit, these buttons are too close :-(

This keeps puzzling me.
If I source the GCLK5 from e.g. FDPLL1 configured to tun at at 16MHz with prescaler 16, all test run fine and the offset in xtimer_usleep is ~33µs, but this is at the expense of a higher power consumption of around 2 mA.

When I use the 48 MHz DFLL I get

• Offset: ~4300µs with GCLK_GENCTRL_DIV(12) & TC_CTRLA_PRESCALER_DIV4
• Offset: ~4300µs with GCLK_GENCTRL_DIV(6) & TC_CTRLA_PRESCALER_DIV8
• Offset: ~5µs with with GCLK_GENCTRL_DIV(3) & TC_CTRLA_PRESCALER_DIV16 but with bursts of 5000µs

With 120 MHz DPLL0 :

• Offset: ~5000µs with GCLK_GENCTRL_DIV(120) & TC_CTRLA_PRESCALER_DIV1
• Offset: ~5000µs with GCLK_GENCTRL_DIV(15) & TC_CTRLA_PRESCALER_DIV8
• Offset: ~5µs with GCLK_GENCTRL_DIV(4) & TC_CTRLA_PRESCALER_DIV16 but with burst of 4600µs - and the clock is wrong.
• Offset: 6µs with GCLK_GENCTRL_DIV(2) & TC_CTRLA_PRESCALER_DIV64 - but now the clock is wrong

Only when I overclock the CPU to 128 MHz I get both a stable and correct clock.

If I source the GCLK5 from e.g. FDPLL1 configured to tun at at 16MHz with prescaler 16, all test run fine and the offset in xtimer_usleep is ~33µs, but this is at the expense of a higher power consumption of around 2 mA.

Enabling a second PLL may not be the best solution especially for the power consumption.

Offset: ~5µs with GCLK_GENCTRL_DIV(4) & TC_CTRLA_PRESCALER_DIV16 but with burst of 4600µs - and the clock is wrong

Could you elaborate which clock and what is wrong there ? I also tried this conf but I don't have a burst of 4600us.

Offset: ~5000µs with GCLK_GENCTRL_DIV(120) & TC_CTRLA_PRESCALER_DIV1

I don't get why we have a so much offset with this config...

Could you elaborate which clock and what is wrong there?

(120 MHz / 4) / 16 = 1.875 MHz - but xtimer expects a 1MHz clock.

same for

(120 MHz / 2) / 64 = 0.9375 MHz

I can't explain the offset either - especially since we are using the same timer to set the alarm and measure the offset.

periph_flashpage should work now.
I made some changes to cpu/sam0_common/include/cpu_conf.h to use values from ASF instead of relying on hard-coded numbers.

I've tested the change on both the same54-xpro & samr21-xpro, the output of info looks correct for both and test_last_raw is working and so is erase.

Interestingly, LOCK_REGIONS differs for each sam0 MCU, but RIOT doesn't seem to use this (or care) at all - it just unlocks each 16 byte block individually, no matter what.

An update on the xtimer situation:

When I add static inline TcCount32 *dev(tim_t tim) __attribute__ ((optimize(0))); to sam0_common/periph/timer.c, the tests are working.

edit: unsigned int timer_read(tim_t tim) __attribute__ ((optimize(0))); works too.

In fact, it looks like a delay is needed between writing TC_CTRLBSET_CMD_READSYNC and reading SYNCBUSY.

I found for (volatile int i = 8; i; --i); to work well enough for that.

The timer tests should work now with #11610 applied.

Here we go