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cpu/esp_common: use ESP-IDF for ESP32 in periph/flash
Updates `cpu/esp_common/periph/flash` for ESP-IDF 4.4. `spi_flash_*` functions for ESP32 are removed since these functions are now used from ESP-IDF.
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3 files changed

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-227
lines changed

3 files changed

+5
-227
lines changed

‎cpu/esp32/esp-idf/include/sdkconfig.h‎

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Original file line numberDiff line numberDiff line change
@@ -181,6 +181,7 @@ extern "C" {
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* SPI Flash driver configuration (DO NOT CHANGE)
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*/
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#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
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#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
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/**
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* Ethernet driver configuration (DO NOT CHANGE)

‎cpu/esp32/esp-idf/spi_flash/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@ ESP32_SDK_SRC = \
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components/driver/spi_common.c \
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components/spi_flash/$(CPU)/flash_ops_$(CPU).c \
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components/spi_flash/$(CPU)/spi_flash_rom_patch.c \
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components/spi_flash/esp_flash_api.c \
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components/spi_flash/partition.c \
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#
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ifeq (,$(filter periph_spi,$(USEMODULE)))

‎cpu/esp_common/periph/flash.c‎

Lines changed: 2 additions & 227 deletions
Original file line numberDiff line numberDiff line change
@@ -220,233 +220,7 @@ void spi_flash_drive_init (void)
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DEBUG("\n");
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}
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223-
#ifdef MCU_ESP32
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#define RETURN_WITH_ESP_ERR_CODE(err) do { \
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switch (err) { \
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case ESP_ROM_SPIFLASH_RESULT_OK : return ESP_OK; \
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case ESP_ROM_SPIFLASH_RESULT_ERR : return ESP_ERR_FLASH_OP_FAIL; \
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case ESP_ROM_SPIFLASH_RESULT_TIMEOUT: return ESP_ERR_FLASH_OP_TIMEOUT; \
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} \
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return ESP_FAIL; \
232-
} while(0)
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static uint32_t _flash_buf[ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM / sizeof(uint32_t)];
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esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size)
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{
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DEBUG("%s addr=%08x size=%u buf=%p\n", __func__, addr, size, buff);
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CHECK_PARAM_RET (buff != NULL, -ENOTSUP);
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/* size must be within the flash address space */
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CHECK_PARAM_RET (addr + size <= _flash_end, -EOVERFLOW);
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int result = ESP_ROM_SPIFLASH_RESULT_OK;
246-
uint32_t len = size;
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/* if addr is not 4 byte aligned, we need to read the first full word */
249-
if (addr & 0x3) {
250-
uint32_t word_addr = addr & ~0x3;
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uint32_t pos_in_word = addr & 0x3;
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uint32_t len_in_word = 4 - pos_in_word;
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len_in_word = (len_in_word < len) ? len_in_word : len;
254-
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
258-
259-
result = esp_rom_spiflash_read(word_addr, _flash_buf, 4);
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memcpy(buff, (uint8_t *)_flash_buf + pos_in_word, len_in_word);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_in_word;
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addr += len_in_word;
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len -= len_in_word;
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}
270-
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/* read all full words, maximum ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM
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in one read operation */
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while (len > 4 && result == ESP_ROM_SPIFLASH_RESULT_OK) {
274-
uint32_t len_full_words = len & ~0x3;
275-
if (len_full_words > ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) {
276-
len_full_words = ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
277-
}
278-
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/* disable interrupts and the cache */
280-
critical_enter();
281-
Cache_Read_Disable(PRO_CPU_NUM);
282-
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result |= esp_rom_spiflash_read(addr, _flash_buf, len_full_words);
284-
memcpy(buff, _flash_buf, len_full_words);
285-
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_full_words;
291-
addr += len_full_words;
292-
len -= len_full_words;
293-
}
294-
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/* if there is some remaining, we need to prepare last word */
296-
if (len && result == ESP_ROM_SPIFLASH_RESULT_OK) {
297-
/* disable interrupts and the cache */
298-
critical_enter();
299-
Cache_Read_Disable(PRO_CPU_NUM);
300-
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result |= esp_rom_spiflash_read(addr, _flash_buf, 4);
302-
memcpy(buff, _flash_buf, len);
303-
304-
/* enable interrupts and the cache */
305-
Cache_Read_Enable(PRO_CPU_NUM);
306-
critical_exit();
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}
308-
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/* return with the ESP-IDF error code that is mapped from ROM error code */
310-
RETURN_WITH_ESP_ERR_CODE(result);
311-
}
312-
313-
esp_err_t IRAM_ATTR spi_flash_write(size_t addr, const void *buff, size_t size)
314-
{
315-
DEBUG("%s addr=%08x size=%u buf=%p\n", __func__, addr, size, buff);
316-
317-
CHECK_PARAM_RET (buff != NULL, -ENOTSUP);
318-
319-
/* size must be within the flash address space */
320-
CHECK_PARAM_RET (addr + size <= _flash_end, -EOVERFLOW);
321-
322-
/* prepare for write access */
323-
int result = esp_rom_spiflash_unlock();
324-
uint32_t len = size;
325-
326-
/* if addr is not 4 byte aligned, we need to prepare first full word */
327-
if (addr & 0x3 && result == ESP_ROM_SPIFLASH_RESULT_OK) {
328-
uint32_t word_addr = addr & ~0x3;
329-
uint32_t pos_in_word = addr & 0x3;
330-
uint32_t len_in_word = 4 - pos_in_word;
331-
len_in_word = (len_in_word < len) ? len_in_word : len;
332-
333-
/* disable interrupts and the cache */
334-
critical_enter();
335-
Cache_Read_Disable(PRO_CPU_NUM);
336-
337-
result |= esp_rom_spiflash_read(word_addr, _flash_buf, 4);
338-
memcpy((uint8_t *)_flash_buf + pos_in_word, buff, len_in_word);
339-
result |= esp_rom_spiflash_write(word_addr, _flash_buf, 4);
340-
341-
/* enable interrupts and the cache */
342-
Cache_Read_Enable(PRO_CPU_NUM);
343-
critical_exit();
344-
345-
buff = (uint8_t*)buff + len_in_word;
346-
addr += len_in_word;
347-
len -= len_in_word;
348-
}
349-
350-
/* write all full words, maximum ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM
351-
in one write operation */
352-
while (len > 4 && result == ESP_ROM_SPIFLASH_RESULT_OK) {
353-
uint32_t len_full_words = len & ~0x3;
354-
if (len_full_words > ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM) {
355-
len_full_words = ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM;
356-
}
357-
358-
/* disable interrupts and the cache */
359-
critical_enter();
360-
Cache_Read_Disable(PRO_CPU_NUM);
361-
362-
memcpy(_flash_buf, buff, len_full_words);
363-
result |= esp_rom_spiflash_write(addr, _flash_buf, len_full_words);
364-
365-
/* enable interrupts and the cache */
366-
Cache_Read_Enable(PRO_CPU_NUM);
367-
critical_exit();
368-
369-
buff = (uint8_t*)buff + len_full_words;
370-
addr += len_full_words;
371-
len -= len_full_words;
372-
}
373-
374-
/* if there is some remaining, we need to prepare last word */
375-
if (len && result == ESP_ROM_SPIFLASH_RESULT_OK) {
376-
/* disable interrupts and the cache */
377-
critical_enter();
378-
Cache_Read_Disable(PRO_CPU_NUM);
379-
380-
result |= esp_rom_spiflash_read(addr, _flash_buf, 4);
381-
memcpy(_flash_buf, buff, len);
382-
result |= esp_rom_spiflash_write(addr, _flash_buf, 4);
383-
384-
/* enable interrupts and the cache */
385-
Cache_Read_Enable(PRO_CPU_NUM);
386-
critical_exit();
387-
}
388-
389-
/* reset write access */
390-
esp_rom_spiflash_lock();
391-
392-
/* return with the ESP-IDF error code that is mapped from ROM error code */
393-
RETURN_WITH_ESP_ERR_CODE(result);
394-
}
395-
396-
#if !IS_USED(MODULE_ESP_IDF_SPI_FLASH)
397-
esp_err_t IRAM_ATTR spi_flash_erase_sector(size_t sector)
398-
{
399-
return spi_flash_erase_range(sector * _flashchip->sector_size, 1);
400-
}
401-
#endif
402-
403-
esp_err_t IRAM_ATTR spi_flash_erase_range(size_t addr, size_t size)
404-
{
405-
/* size must be within the flash address space */
406-
CHECK_PARAM_RET (addr + size <= _flash_end, -EOVERFLOW);
407-
408-
/* size must be a multiple of sector_size && at least one sector */
409-
CHECK_PARAM_RET (size >= _flashchip->sector_size, -ENOTSUP);
410-
CHECK_PARAM_RET (size % _flashchip->sector_size == 0, -ENOTSUP)
411-
412-
/* prepare for write access */
413-
uint32_t result = esp_rom_spiflash_unlock();
414-
415-
/* erase as many sectors as necessary */
416-
uint32_t sec = addr / _flashchip->sector_size;
417-
uint32_t cnt = size / _flashchip->sector_size;
418-
uint32_t sec_per_block = _flashchip->block_size / _flashchip->sector_size;
419-
420-
while (cnt && result == ESP_ROM_SPIFLASH_RESULT_OK) {
421-
/* disable interrupts and the cache */
422-
critical_enter();
423-
Cache_Read_Disable(PRO_CPU_NUM);
424-
425-
/* erase block-wise (64 kByte) if cnt is at least sec_per_block */
426-
if (cnt >= sec_per_block) {
427-
result = esp_rom_spiflash_erase_block (sec / sec_per_block);
428-
sec += sec_per_block;
429-
cnt -= sec_per_block;
430-
}
431-
else {
432-
result = esp_rom_spiflash_erase_sector (sec++);
433-
cnt--;
434-
}
435-
436-
/* enable interrupts and the cache */
437-
Cache_Read_Enable(PRO_CPU_NUM);
438-
critical_exit();
439-
}
440-
441-
/* reset write access */
442-
esp_rom_spiflash_lock();
443-
444-
/* return with the ESP-IDF error code that is mapped from ROM error code */
445-
RETURN_WITH_ESP_ERR_CODE(result);
446-
}
447-
448-
#endif /* MCU_ESP32 */
449-
223+
#ifdef MCU_ESP8266
450224
const esp_partition_t* esp_partition_find_first(esp_partition_type_t type,
451225
esp_partition_subtype_t subtype,
452226
const char* label)
@@ -503,6 +277,7 @@ esp_err_t esp_partition_erase_range(const esp_partition_t* part,
503277

504278
return spi_flash_erase_range(part->address + addr, size);
505279
}
280+
#endif /* MCU_ESP8266 */
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507282
static int _flash_init (mtd_dev_t *dev)
508283
{

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