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dyladdylad
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cpu/sam0: remove bitfield usage in sdhc driver
Signed-off-by: Dylan Laduranty <[email protected]>
1 parent 04e4770 commit ccc155e

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1 file changed

+18
-13
lines changed
  • cpu/sam0_common/sam0_sdhc

1 file changed

+18
-13
lines changed

‎cpu/sam0_common/sam0_sdhc/sdhc.c‎

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -106,14 +106,19 @@ static bool sdio_test_type(sdhc_state_t *state);
106106

107107
static bool _card_detect(sdhc_state_t *state)
108108
{
109-
return state->dev->PSR.bit.CARDINS;
109+
return state->dev->PSR.reg & SDHC_PSR_CARDINS;
110110
}
111111

112112
static inline void _clock_sdcard(sdhc_state_t *state, bool on)
113113
{
114114
(void)state;
115115

116-
SDHC_DEV->CCR.bit.SDCLKEN = on;
116+
if (on) {
117+
SDHC_DEV->CCR.reg |= SDHC_CCR_SDCLKEN;
118+
}
119+
else {
120+
SDHC_DEV->CCR.reg &= ~SDHC_CCR_SDCLKEN;
121+
}
117122
}
118123

119124
static bool _check_mask(uint32_t val, uint32_t mask)
@@ -230,7 +235,7 @@ static void _init_clocks(sdhc_state_t *state)
230235
| GCLK_PCHCTRL_GEN(SDHC_CLOCK);
231236
GCLK->PCHCTRL[SDHC0_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_CHEN
232237
| GCLK_PCHCTRL_GEN(SDHC_CLOCK_SLOW);
233-
MCLK->AHBMASK.bit.SDHC0_ = 1;
238+
MCLK->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
234239
isr_ctx_0 = state;
235240
NVIC_EnableIRQ(SDHC0_IRQn);
236241
}
@@ -249,7 +254,7 @@ static void _init_clocks(sdhc_state_t *state)
249254
| GCLK_PCHCTRL_GEN(SDHC_CLOCK);
250255
GCLK->PCHCTRL[SDHC1_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_CHEN
251256
| GCLK_PCHCTRL_GEN(SDHC_CLOCK_SLOW);
252-
MCLK->AHBMASK.bit.SDHC1_ = 1;
257+
MCLK->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
253258
isr_ctx_1 = state;
254259
NVIC_EnableIRQ(SDHC1_IRQn);
255260
}
@@ -370,7 +375,7 @@ int sdhc_init(sdhc_state_t *state)
370375
_set_hc(state);
371376

372377
/* if it is high speed capable, (well it is) */
373-
if (IS_USED(SDHC_ENABLE_HS) && SDHC_DEV->CA0R.bit.HSSUP) {
378+
if (IS_USED(SDHC_ENABLE_HS) && (SDHC_DEV->CA0R.reg & SDHC_CA0R_HSSUP)) {
374379
if (!_test_high_speed(state)) {
375380
res = -EIO;
376381
goto out;
@@ -441,7 +446,7 @@ bool sdhc_send_cmd(sdhc_state_t *state, uint32_t cmd, uint32_t arg)
441446
do {
442447
if (--timeout == 0) {
443448
SDHC_DEV->SRR.reg = SDHC_SRR_SWRSTCMD; /* reset command */
444-
while (SDHC_DEV->SRR.bit.SWRSTCMD) {}
449+
while (SDHC_DEV->SRR.reg & SDHC_SRR_SWRSTCMD) {}
445450
return false;
446451
}
447452
} while (!(SDHC_DEV->PSR.reg & SDHC_PSR_DATLL(1))); /* DAT[0] is busy bit */
@@ -454,7 +459,7 @@ static void _set_speed(sdhc_state_t *state, uint32_t fsdhc)
454459
{
455460
(void)state;
456461

457-
if (SDHC_DEV->CCR.bit.SDCLKEN) {
462+
if (SDHC_DEV->CCR.reg & SDHC_CCR_SDCLKEN) {
458463
/* wait for command/data to go inactive */
459464
while (SDHC_DEV->PSR.reg & (SDHC_PSR_CMDINHC | SDHC_PSR_CMDINHD)) {}
460465
/* disable the clock */
@@ -469,8 +474,8 @@ static void _set_speed(sdhc_state_t *state, uint32_t fsdhc)
469474
/* write the 10 bit clock divider */
470475
SDHC_DEV->CCR.reg = SDHC_CCR_SDCLKFSEL(div) | SDHC_CCR_USDCLKFSEL(div >> 8)
471476
| SDHC_CCR_CLKGSEL | SDHC_CCR_INTCLKEN;
472-
while (!SDHC_DEV->CCR.bit.INTCLKS) {} /* wait for clock to be stable */
473-
SDHC_DEV->CCR.bit.SDCLKEN = 1; /* enable clock to card */
477+
while (!(SDHC_DEV->CCR.reg & SDHC_CCR_INTCLKS)) {} /* wait for clock to be stable */
478+
SDHC_DEV->CCR.reg |= SDHC_CCR_SDCLKEN; /* enable clock to card */
474479
}
475480

476481
/**
@@ -487,7 +492,7 @@ static void _set_hc(sdhc_state_t *state)
487492
else {
488493
SDHC_DEV->HC1R.reg &= ~SDHC_HC1R_HSEN;
489494
}
490-
if (!SDHC_DEV->HC2R.bit.PVALEN) { /* PVALEN is probably always low */
495+
if (!(SDHC_DEV->HC2R.reg & SDHC_HC2R_PVALEN)) { /* PVALEN is probably always low */
491496
_set_speed(state, state->clock);
492497
}
493498
if (state->bus_width == 4) {
@@ -755,7 +760,7 @@ static bool _init_transfer(sdhc_state_t *state, uint32_t cmd, uint32_t arg, uint
755760
do {
756761
if (--timeout == 0) {
757762
SDHC_DEV->SRR.reg = SDHC_SRR_SWRSTCMD; /* reset command */
758-
while (SDHC_DEV->SRR.bit.SWRSTCMD) {}
763+
while (SDHC_DEV->SRR.reg & SDHC_SRR_SWRSTCMD) {}
759764
return false;
760765
}
761766
} while (!(SDHC_DEV->PSR.reg & SDHC_PSR_DATLL(1))); /* DAT[0] is busy bit */
@@ -830,7 +835,7 @@ int sdhc_read_blocks(sdhc_state_t *state, uint32_t address, void *dst, uint16_t
830835

831836
int num_words = (num_blocks * SD_MMC_BLOCK_SIZE) / 4;
832837
for (int words = 0; words < num_words; words++) {
833-
while (!SDHC_DEV->PSR.bit.BUFRDEN) {}
838+
while (!(SDHC_DEV->PSR.reg & SDHC_PSR_BUFRDEN)) {}
834839
*p++ = SDHC_DEV->BDPR.reg;
835840
}
836841

@@ -916,7 +921,7 @@ int sdhc_write_blocks(sdhc_state_t *state, uint32_t address, const void *src,
916921
/* Write data */
917922
int num_words = (num_blocks * SD_MMC_BLOCK_SIZE) / 4;
918923
for (int words = 0; words < num_words; words++) {
919-
while (!SDHC_DEV->PSR.bit.BUFWREN) {}
924+
while (!(SDHC_DEV->PSR.reg & SDHC_PSR_BUFWREN)) {}
920925
SDHC_DEV->BDPR.reg = *p++;
921926
}
922927

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