cpu/esp32: update of ld script for littlefs*

gschorcht · gschorcht · commit 5b4389cf46ac · 2020-02-22T01:35:07.000+01:00
During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.
diff --git a/cpu/esp32/ld/esp32.common.ld b/cpu/esp32/ld/esp32.common.ld
@@ -101,11 +101,13 @@ SECTIONS
     *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)
     /* parts of RIOT that should to run in IRAM */
     *core.a:*(.literal .text .literal.* .text.*)
+    *littlefs.a:*(.literal .text .literal.* .text.*)
+    *littlefs2.a:*(.literal .text .literal.* .text.*)
     *spiffs_fs.a:*(.literal .text .literal.* .text.*)
     *spiffs.a:*(.literal .text .literal.* .text.*)
     *vfs.a:*(.literal .text .literal.* .text.*)
 
-    /* part of RIOT ports that should run in IRAM */
+    /* part of the RIOT port that should run in IRAM */
     *cpu.a:*(.literal .text .literal.* .text.*)
     *periph.a:*(.literal .text .literal.* .text.*)
     *mtd.a:**(.literal .text .literal.* .text.*)
