cpu/stm32f2: fix sampling time for VBat

crasbe · crasbe · commit 596670bdde43 · 2025-04-02T21:38:29.000+02:00
diff --git a/cpu/stm32/periph/adc_f2.c b/cpu/stm32/periph/adc_f2.c
@@ -96,6 +96,13 @@ int adc_init(adc_t line)
     assume((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX);
     ADC->CCR = ((clk_div / 2) - 1) << 16;
 
+    if (IS_USED(MODULE_PERIPH_VBAT)) {
+        /* Set the sampling rate for the VBat channel to 112 cycles. It reads
+        * correct with 84 cycles already, so this adds some margin. */
+        ADC1->SMPR1 = (ADC1->SMPR1 & ~ADC_SMPR1_SMP18) | \
+                      (ADC_SMPR1_SMP18_2 | ADC_SMPR1_SMP18_0);
+    }
+
     /* enable the ADC module */
     dev(line)->CR2 = ADC_CR2_ADON;
 
