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lines changed Original file line number Diff line number Diff line change 1+ # UART @ 115200 Bd is not reliable with a CPU clock of ~ 5 MHz, occasionally
2+ # chars get lost. Adding an 8 MHz crystal or an external resistor so that the
3+ # DCO can reach 8 MHz does yield the speed bump needed for a more reliable
4+ # UART connection @ 115200 Bd
5+ BAUD ?= 9600
6+
17# When freshly plugged in the Olimex MSP430-JTAG-Tiny debugger provides a
28# ttyACM interface, which is only available until the first flashing. A
39# `make term` or even a `make flash term` may pick the JTAG debugger instead
@@ -16,3 +22,4 @@ TTY_SELECT_CMD := $(RIOTTOOLS)/usb-serial/ttys.py \
1622 --format path serial
1723
1824include $(RIOTBOARD)/common/msp430/Makefile.include
25+ CFLAGS += -DSTDIO_UART_BAUDRATE=$(BAUD)
Original file line number Diff line number Diff line change @@ -35,6 +35,10 @@ extern "C" {
3535 * @brief Clock configuration
3636 */
3737static const msp430_clock_params_t clock_params = {
38+ /* Without an external resistor, the DCO frequency typically tops out
39+ * at something like 5 MHz. However, the DCO calibration just picks the
40+ * closet possible value, in this case it will go for the highest frequency
41+ * the silicon at hand can run at. */
3842 .target_dco_frequency = MHZ (8 ),
3943 .lfxt1_frequency = 32768 ,
4044 .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK ,
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