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Fix ARM NEON VQABS and VQNEG instruction decoding - #10114
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ryanmkurtz
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Feature: Processor/ARM
Status: Triage
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You used I'm confused about the comment to "Update ARM SLEIGH definitions for D and Q registers"? I think the changes to ARMAssemblyTest are excessive. We really don't need to that many tests for two instructions. Otherwise we would have hundreds of thousands of instruction assembly tests. |
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Hi @GhidorahRex, Thank you for the detailed review.
I also rebuilt the ARM SLEIGH definitions and reran Thanks again for your guidance. I'm happy to make any further adjustments. |
GhidorahRex
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Status: Internal
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Summary
Fix two ARM NEON instruction-decoding issues:
VectorNegpcodeop for signed-integer VQNEG operations, replacing the inappropriate use ofFloatVectorNeg.The changes adjust ARM NEON instruction constructors and pcode behavior. They do not redefine the D or Q registers.
Validation
git diff --check— Passed.ARMAssemblyTest— BUILD SUCCESSFUL, including all four retained regression tests.4e c7 b0 f3vqabs.s8 q6,q7ce c7 b0 f3vqneg.s8 q6,q7Development Note
AI assistance was used during development and revision. I reviewed and applied the changes, executed the compilation and regression tests locally, and submitted the validated implementation.
Related Issues
Fixes #10110
Fixes #10111