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Provide make_tma_descriptor, DLPack -> CUtensorMap - #6237

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fbusato merged 66 commits into
NVIDIA:mainfrom
fbusato:cuda-dlpack
Nov 17, 2025
Merged

fbusato merged 66 commits into
NVIDIA:mainfrom
fbusato:cuda-dlpack

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@fbusato fbusato commented Oct 14, 2025 •

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Address #6172

Description

Provide make_tma_descriptor to convert DLTensor and DLManagedTensor to CUtensorMap.

Aspects discussed with the JAX team:

  • Interface: current APIs are fine.
  • Error handling: Exceptions should be avoided.

Aspects to discuss:

  • CUtensorMap opaque type is enough, or do we need a higher-level object type.

Todo:

  • extend unit test
  • documentation

@fbusato fbusato self-assigned this Oct 14, 2025
@fbusato fbusato added this to CCCL Oct 14, 2025
@fbusato fbusato added the 3.2.0 label Oct 14, 2025
@github-project-automation github-project-automation Bot moved this to Todo in CCCL Oct 14, 2025
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@cccl-authenticator-app cccl-authenticator-app Bot moved this from Todo to In Progress in CCCL Oct 14, 2025
@fbusato fbusato changed the title [Early Draft] Provide make_tma_descriptor, DLPack -> CUtensorMap Provide make_tma_descriptor, DLPack -> CUtensorMap Oct 20, 2025
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fbusato marked this pull request as ready for review October 21, 2025 21:54
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fbusato requested a review from a team as a code owner October 21, 2025 21:54
@oleksandr-pavlyk

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My original example created DLTensor for square matrix with C contiguous layout, data type float, and shape (256, 256).

When passing DLTensor with shape {57, 57}, strides {57, 1} (C-contiguous layout), the assertion make_tma_descriptor.h:398: __get_tensor_strides: Assertion `Stride in bytes is not a multiple of the alignment (32 or 16)' failed. is triggered.

Replacing 57 with 58 also trips it, but 56 works:

>>> [ (n, (n * 4) % 16) for n in [55, 56, 57, 58] ]
[(55, 12), (56, 0), (57, 4), (58, 8)]

Passing tma_oob_fill::nan does not help.

All tests appear to use shape values that are a whole multiple of itemsize.

While this may be what is expected by the driver, I feel we need to provide an example/suggestion of how to handle layouts were the stride in GMEM is not a multiple of 16 bytes.

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When passing DLTensor with shape {57, 57}, strides {57, 1} (C-contiguous layout), the assertion make_tma_descriptor.h:398: __get_tensor_strides: Assertion `Stride in bytes is not a multiple of the alignment (32 or 16)' failed. is triggered.

The __CCCL_VERIFY should use matching quotation symbols. Note how the output above uses ` and ' instead of ' and '.

@fbusato

fbusato commented Nov 7, 2025

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The __CCCL_VERIFY should use matching quotation symbols. Note how the output above uses ` and ' instead of ' and '.

_CCCL_VERIFY relies on __assert_fail so it is no a related to CCCL

@fbusato

fbusato commented Nov 7, 2025

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My original example created DLTensor for square matrix with C contiguous layout, data type float, and shape (256, 256).

When passing DLTensor with shape {57, 57}, strides {57, 1} (C-contiguous layout), the assertion make_tma_descriptor.h:398: __get_tensor_strides: Assertion `Stride in bytes is not a multiple of the alignment (32 or 16)' failed. is triggered.

Replacing 57 with 58 also trips it, but 56 works:

[ (n, (n * 4) % 16) for n in [55, 56, 57, 58] ]
[(55, 12), (56, 0), (57, 4), (58, 8)]
Passing tma_oob_fill::nan does not help.

The behavior seems correct. Note the message Stride in BYTES is not a multiple of the alignment ... : 56 * sizeof(int) % 16 == 0.

All tests appear to use shape values that are a whole multiple of itemsize.

While this may be what is expected by the driver, I feel we need to provide an example/suggestion of how to handle layouts were the stride in GMEM is not a multiple of 16 bytes.

This is not possible. 16 bytes is a constraint of the HW

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+1 for the device_ref changes

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Comment thread docs/libcudacxx/extended_api/tma.rst Resolved
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@fbusato
fbusato enabled auto-merge (squash) November 14, 2025 23:37
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@miscco this PR is blocked by you. Can you please re-review and unblock? Thx!

Comment on lines +202 to +205
// auto __current_device = ::cuda::__driver::__deviceGet(__tensor.device.device_id);
// auto __compute_capability =
// ::cuda::__driver::__deviceGetAttribute(::CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR, __current_device);
//_CCCL_VERIFY(__compute_capability >= 9, "Compute capability 9.0 or higher is required");

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Please drop dead code

// auto __compute_capability =
// ::cuda::__driver::__deviceGetAttribute(::CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR, __current_device);
//_CCCL_VERIFY(__compute_capability >= 9, "Compute capability 9.0 or higher is required");
if (__compute_capability >= 10)

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previously __compute_capability was 90. now this is 10 are we missing a zero or did something change

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it was automatically merged. Let me open a new PR

@fbusato
fbusato merged commit 91c8497 into NVIDIA:main Nov 17, 2025
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@github-project-automation github-project-automation Bot moved this from In Review to Done in CCCL Nov 17, 2025
Comment on lines +513 to +516
tma_interleave_layout __interleave_layout = tma_interleave_layout::none,
tma_swizzle __swizzle = tma_swizzle::none,
tma_l2_fetch_size __l2_fetch_size = tma_l2_fetch_size::none,
tma_oob_fill __oobfill = tma_oob_fill::none) noexcept

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Q: I don't know anything about tma, but if I want to specify only l2 fetch size, then I have to type make_tma_descriptor(..., tma_interleave_layout::none, tma_swizzle::none, tma_l2_fetch_size::some_size)?

If yes, my question is whether it wouldn't be better to implement this as a separate struct tma_descriptor_params (or some other name) and in C++20 you could do: make_tma_descriptor(..., {.l2_fetch_size = tma_l2_fetch_size::some_size})

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That looks cool!

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Actually, with all compilers (except for msvc) it works even in C++17, see https://godbolt.org/z/jh3vT4fc4

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this is a very nice idea. Unfortunate, C++20 is not really adopted in the API context, so the modification would make the API less user-friendly. We can think about it in the future.

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But as I said, nvcc has no problem with the code, nor do any of the other compilers with exception of msvc. So most of the time, you can just use it in C++17 as well. And if not, you just have to fallback to:

make_tma_descriptor(..., {tma_interleave_layout::none, tma_swizzle::none, tma_l2_fetch_size::some_size});

which is basically the same thing.

Please, reconsider this

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