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[None][feat] Add FP8 rowwise GEMMs for B200 #8332
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📝 WalkthroughWalkthroughThis PR adds SM100 architecture support to the FP8 rowwise GEMM kernels. Changes include enabling SM100 compilation in CMake, introducing SM100-specific kernel templates and dispatch routing logic, implementing the SM100 device GEMM structure, and removing a Blackwell skip decorator from tests. Changes
Sequence Diagram(s)sequenceDiagram
participant Caller
participant DispatchRouter as dispatchToArch
participant SM100Path as SM100 Path
participant SM90Path as SM89/90/120f Path
Caller->>DispatchRouter: Check mSm value
alt mSm == 100
DispatchRouter->>SM100Path: Call dispatchGemmToCutlassSm100
SM100Path->>SM100Path: Select SM100 tile shapes<br/>and cluster config
SM100Path->>SM100Path: Call dispatchGemmConfigSm100
SM100Path->>SM100Path: Launch DeviceGemmFp8RowwiseSm100<br/>kernel with SM100 guard
SM100Path-->>Caller: Return
else Other SM versions
DispatchRouter->>SM90Path: Route to existing<br/>SM89/90/120f logic
SM90Path-->>Caller: Return
end
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes Pre-merge checks and finishing touches❌ Failed checks (2 warnings)
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🧹 Nitpick comments (1)
cpp/tensorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_kernel_template_sm89.h (1)
109-118: LGTM! Compile-time check correctly expanded for B200 support.The conditional now properly includes SM10x (SM100-109) devices in addition to SM89 and SM12x, and the error message accurately reflects "Blackwell devices." The logic aligns with the runtime dispatch changes in
fp8_rowwise_gemm_template.h.Optional: Consider renaming the struct.
The struct name
Sm89_12xOnlyis now slightly misleading since it also supports SM10x devices. A name likeSm89_Blackwellwould be more accurate, though this is a low-priority refactor.
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cpp/tensorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_kernel_template_sm89.h (3)
cpp/tensorrt_llm/kernels/cutlass_kernels/fp4_gemm/mxfp8_mxfp4_gemm_template_sm100.h (2)
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cpp/tensorrt_llm/kernels/cutlass_kernels/CMakeLists.txt (1)
203-203: LGTM! B200 architecture support added correctly.The addition of
100fto the CUDA architectures enables FP8 rowwise GEMM compilation for SM100 (B200) devices with forward compatibility.tests/unittest/_torch/thop/parallel/test_fp8_rowwise_linear.py (1)
3-3: LGTM! Test now enabled for Blackwell devices.Removing the
skip_blackwellimport allows this test to run on B200 and other Blackwell devices, providing appropriate test coverage for the new FP8 rowwise GEMM support.cpp/tensorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_template.h (1)
511-511: Verify SM100+ devices should use SM89 implementation.The dispatch logic now routes SM100+ devices (including B200 and SM120+) to the SM89 kernel implementation, while SM90 continues using TMA-based kernels. This appears intentional, but please confirm:
- SM100 (B200) devices lack TMA-based FP8 rowwise kernels and should use SM89 implementation?
- SM120+ devices should also use SM89 implementation rather than dedicated SM120 kernels?
The changes are consistent across both
dispatchToArch(Line 511) andgetConfigs(Line 578) methods.Also applies to: 578-578
cpp/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp (1)
178-178: LGTM! Tile configuration heuristics updated for B200 support.The candidate tile selection for FP8 GEMMs now correctly includes SM100+ devices alongside SM89, ensuring they receive appropriate tile configurations. This change aligns with the dispatch logic updates in
fp8_rowwise_gemm_template.h.Also applies to: 196-196
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Actionable comments posted: 1
🧹 Nitpick comments (1)
cpp/tensorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_kernel_template_sm100.h (1)
95-111: Epilogue types reuse Sm90 fusion on SM100 — confirm CUTLASS compatibility.Using Sm90* fusion components on SM100 is common but depends on CUTLASS version. Please confirm these aliases remain valid for arch::Sm100 to avoid template selection drift.
If CUTLASS exposes SM100‑specific aliases later, consider switching for clarity.
Also applies to: 121-136
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📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
PR: NVIDIA/TensorRT-LLM#7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
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[error] 24-24: 'cute/tensor.hpp' file not found
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🔇 Additional comments (3)
cpp/tensorrt_llm/kernels/cutlass_kernels/CMakeLists.txt (1)
203-203: Enable SM100 builds for FP8 rowwise GEMM — looks good.Including 100f on fb_gemm_src matches the new SM100 path. Please verify CI covers 100-real and that CUTLASS for 100 is available in the toolchain.
tests/unittest/_torch/thop/parallel/test_fp8_rowwise_linear.py (1)
3-3: Removing Blackwell skip is appropriate for SM100 enablement.Confirm CI runs this test on SM100/SM120 runners; keep skip_pre_hopper to avoid pre‑Hopper devices.
cpp/tensorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_template.h (1)
41-41: SM100 FP8 rowwise GEMM wiring — LGTM with a few checks.
- New include and SM100 prepare/launcher/dispatch paths mirror SM90 patterns; arguments/strides look consistent.
- getConfigs adds comprehensive SM100 tiles and cluster shapes; routing mSm==100 is correct.
Please verify:
- Kernel schedules AUTO work well on SM100 with these tiles; no missing shared‑mem opt‑in paths for large tiles.
- Ktile constants (128, 256)/sizeof(T) match CUTLASS expectations for FP8 rowwise on SM100.
- CI covers workspace‑size path (A/B/D null) for at least one config per cluster shape.
Also applies to: 487-519, 521-549, 551-589, 591-662, 689-693, 761-790
...nsorrt_llm/kernels/cutlass_kernels/fp8_rowwise_gemm/fp8_rowwise_gemm_kernel_template_sm100.h
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New Features
Tests
Description
Add FP8 rowwise GEMMs for B200
Test Coverage
test_fp8_rowwise_linear
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/bot [-h|--help]to print this help message.See details below for each supported subcommand.
run [--reuse-test (optional)pipeline-id --disable-fail-fast --skip-test --stage-list "A10-PyTorch-1, xxx" --gpu-type "A30, H100_PCIe" --test-backend "pytorch, cpp" --add-multi-gpu-test --only-multi-gpu-test --disable-multi-gpu-test --post-merge --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" --detailed-log --debug(experimental)]Launch build/test pipelines. All previously running jobs will be killed.
--reuse-test (optional)pipeline-id(OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.--disable-reuse-test(OPTIONAL) : Explicitly prevent the pipeline from reusing build artifacts and skipping successful test stages from a previous pipeline. Ensure that all builds and tests are run regardless of previous successes.--disable-fail-fast(OPTIONAL) : Disable fail fast on build/tests/infra failures.--skip-test(OPTIONAL) : Skip all test stages, but still run build stages, package stages and sanity check stages. Note: Does NOT update GitHub check status.--stage-list "A10-PyTorch-1, xxx"(OPTIONAL) : Only run the specified test stages. Examples: "A10-PyTorch-1, xxx". Note: Does NOT update GitHub check status.--gpu-type "A30, H100_PCIe"(OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.--test-backend "pytorch, cpp"(OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.--only-multi-gpu-test(OPTIONAL) : Only run the multi-GPU tests. Note: Does NOT update GitHub check status.--disable-multi-gpu-test(OPTIONAL) : Disable the multi-GPU tests. Note: Does NOT update GitHub check status.--add-multi-gpu-test(OPTIONAL) : Force run the multi-GPU tests in addition to running L0 pre-merge pipeline.--post-merge(OPTIONAL) : Run the L0 post-merge pipeline instead of the ordinary L0 pre-merge pipeline.--extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx"(OPTIONAL) : Run the ordinary L0 pre-merge pipeline and specified test stages. Examples: --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx".--detailed-log(OPTIONAL) : Enable flushing out all logs to the Jenkins console. This will significantly increase the log volume and may slow down the job.--debug(OPTIONAL) : Experimental feature. Enable access to the CI container for debugging purpose. Note: Specify exactly one stage in thestage-listparameter to access the appropriate container environment. Note: Does NOT update GitHub check status.For guidance on mapping tests to stage names, see
docs/source/reference/ci-overview.mdand the
scripts/test_to_stage_mapping.pyhelper.kill
killKill all running builds associated with pull request.
skip
skip --comment COMMENTSkip testing for latest commit on pull request.
--comment "Reason for skipping build/test"is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.reuse-pipeline
reuse-pipelineReuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.