[core] Removed extra redundant condition checks (#2615).

ethouris · web-flow · commit 30f6f6bcf239 · 2023-01-25T11:36:34.000+01:00
diff --git a/srtcore/fec.cpp b/srtcore/fec.cpp
@@ -453,7 +453,9 @@ void FECFilterBuiltin::feedSource(CPacket& packet)
     HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo() << " rowoff=" << baseoff
             << " column=" << vert_gx << " .base=%" << vert_base << " coloff=" << vert_off);
 
-    if (vert_off >= 0 && sizeCol() > 1)
+    // [[assert sizeCol() >= 2]]; // see the condition above.
+
+    if (vert_off >= 0)
     {
         // BEWARE! X % Y with different signedness upgrades int to unsigned!
 
@@ -468,7 +470,7 @@ void FECFilterBuiltin::feedSource(CPacket& packet)
             return;
         }
 
-        SRT_ASSERT(vert_off >= 0);
+        // [[assert vert_off >= 0]]; // this condition branch
         int vert_pos = vert_off / int(sizeRow());
 
         HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo()
@@ -496,7 +498,6 @@ void FECFilterBuiltin::feedSource(CPacket& packet)
     }
     else
     {
-
         HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo()
                 << " B:%" << baseoff << " H:*[" << horiz_pos << "] V(B=%" << vert_base
                 << ")[col=" << vert_gx << "]<NO-COLUMN>"

Original file line number	Diff line number	Diff line change
`@@ -453,7 +453,9 @@ void FECFilterBuiltin::feedSource(CPacket& packet)`
`453`	`453`	`HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo() << " rowoff=" << baseoff`
`454`	`454`	`<< " column=" << vert_gx << " .base=%" << vert_base << " coloff=" << vert_off);`
`455`	`455`
`456`		`- if (vert_off >= 0 && sizeCol() > 1)`
	`456`	`+ // [[assert sizeCol() >= 2]]; // see the condition above.`
	`457`	`+`
	`458`	`+ if (vert_off >= 0)`
`457`	`459`	`{`
`458`	`460`	`// BEWARE! X % Y with different signedness upgrades int to unsigned!`
`459`	`461`
`@@ -468,7 +470,7 @@ void FECFilterBuiltin::feedSource(CPacket& packet)`
`468`	`470`	`return;`
`469`	`471`	`}`
`470`	`472`
`471`		`- SRT_ASSERT(vert_off >= 0);`
	`473`	`+ // [[assert vert_off >= 0]]; // this condition branch`
`472`	`474`	`int vert_pos = vert_off / int(sizeRow());`
`473`	`475`
`474`	`476`	`HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo()`
`@@ -496,7 +498,6 @@ void FECFilterBuiltin::feedSource(CPacket& packet)`
`496`	`498`	`}`
`497`	`499`	`else`
`498`	`500`	`{`
`499`		`-`
`500`	`501`	`HLOGC(pflog.Debug, log << "FEC:feedSource: %" << packet.getSeqNo()`
`501`	`502`	`<< " B:%" << baseoff << " H:*[" << horiz_pos << "] V(B=%" << vert_base`
`502`	`503`	`<< ")[col=" << vert_gx << "]<NO-COLUMN>"`