Add T-HEAD's RISC-V CPU E906, Support E906(rv32imac), E906F(rv32imafc),E906FD(rv32imafdc) #344
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…), E906FD(rv32imafdc)
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Thanks for this. If I understand correctly this is adding floating point support. Is there anything non-standard about the floating point code in your chip? If not, would we be better off moving this code to be a build option within the main port rather than as a header file that implements an extension? That way it would work for all compliant RISC-V parts. |
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Thank you very much for your reply, I very much agree with your point of view. |
This adds support for the following: E906(rv32imac), E906F(rv32imafc) and E906FD(rv32imafdc). This change was originally contributed here: FreeRTOS/FreeRTOS-Kernel#344 Signed-off-by: Gaurav Aggarwal <[email protected]>
This adds support for the following: E906(rv32imac), E906F(rv32imafc) and E906FD(rv32imafdc). This change was originally contributed here: FreeRTOS/FreeRTOS-Kernel#344 Signed-off-by: Gaurav Aggarwal <[email protected]>
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Moved this port to the Community Supported Ports repository - FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports#3 Thank you for your contribution. |
* Rename PKCS files to core. * Pin latest corePKCS11 release.
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[New CPU]Add Alibaba T-HEAD's RISC-V CPU E906, Support E906(rv32imac), E906F(rv32imafc),E906FD(rv32imafdc)
Description
T-head Semiconductor Co., Ltd. (Alibaba), the latest commercial RISCV CPU series, The same code, supports 3 types isa： rv32imac, rv32imafc, rv32imafdc. Between different isa, separated by the built-in macro(__riscv_flen) of the toolchain.
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