I would be quite afraid of enabling this by default for f64 as is - seems like a ton of extra overhead if there's little depending on it and those that do could probably get deal with f80?.

This could likely be a lot better off in the f64 case using the IOC FPSR flag and somehow keeping track of when that is clobbered in order to flush it at appropriate times - from a brief check it seems to match the x86 behaviour here and would come for free. It would require basically redoing the bulk of your changes though which isn't the best, even if the result would probably be simpler.

Depends what others think, but might make sense to get the f80 side of this split-up and merged and the rest later? Since that's a lot simpler and 'free'

Yeah, I agree with you. I will split this into F80 and F64. I was not aware of the IOC FPSR flag. Will take a look after the split and rework the F64 part. Thanks for the quick turnaround.

It should be noted that FP exceptions are optional in ARM spec so not all CPU cores implement it. I believe Apple Silicon and Oryon support it, but Cortex doesn't? We do have a check if the feature is supported that is currently unused although.

Even if exceptions aren't implemented, IOC should still be set I think? That would be the main thing here

Good shout, I didn't check if the exception is disabled (or forced to zero by unsupported), if the sticky bit changes or not.

I have updated this PR to focus on F80 (non reduced precision).

I will add a further PR based on this one to add the work for F64.

ping @bylaws