Skip to content

code highlighting issue in vhdl single quote (') #106

@f-mohsen

Description

@f-mohsen

hello
I'm using the plugin with VHDL language, in new version there is some problem with single quote attribute syntax

there is no need to apply highlighting to this kind of syntax, for example error occur in line 2 (Input'length)
plugin look for ending quote pair, but there is no ending pair --> (Input'length') is incorrect

function LeadOneDetector(Input : std_logic_vector) return integer is constant LEN : integer := Input'length; variable Idx : integer range 0 to LEN-1; begin Idx := 0; looop: for i in 0 to LEN-1 loop if Input(i) = '1' then Idx := i; end if; end loop; return Idx; end function LeadOneDetector;

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions