* Add ARM64 Voodoo JIT codegen scaffolding (Phase 1)

Create vid_voodoo_codegen_arm64.h with:
- voodoo_arm64_data_t struct mirroring x86-64 layout
- 292 ARM64 instruction encoding macros (GPR + NEON)
- Struct offset constants for JIT field access
- NEON lookup tables (alookup, aminuslookup, bilinear_lookup)
- voodoo_codegen_init/close for executable memory management
- voodoo_get_block with W^X toggle + I-cache flush
- voodoo_generate with prologue/epilogue (save/restore callee-saved
  GPRs x19-x28, FP/LR, NEON d8-d13; load pinned constants; pixel
  loop skeleton with x-coordinate increment and loop branch)

Guard changes:
- vid_voodoo_render.h: add __aarch64__/_M_ARM64 to NO_CODEGEN gate
- vid_voodoo_render.c: add ARM64 include path for new codegen header

Also add planning docs, build script, and changelog.


* Add compile-time static assertions for all struct offset constants

Verify all 50 STATE_* and PARAMS_* offset constants against actual
offsetof() values using _Static_assert. This catches any layout
differences between assumed and actual struct layouts at compile time.

All assertions pass on ARM64 (Apple Silicon, LP64).


* Update checklist: mark Phase 1 items complete (build verified)

All scaffolding items done except runtime test. Build passes with
all struct offset assertions verified at compile time.


* Mark agent verification checklist item complete


* Fix missing stdint.h include in ARM64 codegen header

Add #include <stdint.h> to vid_voodoo_codegen_arm64.h to resolve
uint8_t, uint16_t, uint32_t type errors. Build now passes cleanly.


* Update changelog with Phase 1 build fix

Document stdint.h fix and build verification.


* Phase 1 complete: runtime test passed

- Add clean-build-and-sign.sh script for full clean builds
- Mark Phase 1 runtime test as complete in checklist
- Document runtime test success in changelog

Runtime test verified: emulator launches, Voodoo initializes,
rendering falls through to interpreter (as expected - pixel
pipeline not yet implemented).

Phase 1 is now 100% complete. Ready for Phase 2.

R2-23: EMIT_MOV_IMM64, EMIT_LOAD_NEON_CONST, and dither_rb_addr now
skip zero halfwords -- MOVZ targets the first non-zero halfword, then
MOVK only for remaining non-zero ones. Saves ~10 instructions per
block across 4 sites (7 prologue ptrs + 3 NEON consts + 1 dither ptr).
New ARM64_MOVZ_X_HW(d, imm16, hw) encoding macro added.

R2-09: (1<<48) dividend for perspective W division now uses a single
MOVZ X4, #1, LSL 86Box#48 instead of 4 instructions (MOVZ #0 + 3 MOVK).
Saves 3 instructions per perspective-textured block.