Update SimSIMD to fix MSan false positive with SVE predicated loads#98966
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alexey-milovidov merged 1 commit intomasterfrom Mar 8, 2026
Merged
Update SimSIMD to fix MSan false positive with SVE predicated loads#98966alexey-milovidov merged 1 commit intomasterfrom
alexey-milovidov merged 1 commit intomasterfrom
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`simsimd_capabilities` probes SIMD functions with `n=0` using a tiny
8-byte dummy buffer. SVE functions use `do { } while (i < n)` loops
that execute once even with n=0, and MSan instruments predicated loads
as full-width vector reads. Enlarged the buffer to 256 bytes to cover
the widest SVE vector (2048 bits).
CI report: https://s3.amazonaws.com/clickhouse-test-reports/json.html?PR=98677&sha=a1b9d7f6170c510431fce962a869aa617d88d888&name_0=PR&name_1=Stress%20test%20%28arm_msan%29
Changelog category: CI Fix or Improvement
Changelog entry: Fix MSan false positive in SimSIMD SVE predicated loads.
Co-Authored-By: Claude Opus 4.6 <[email protected]>
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Summary
simsimd_capabilitiesprobes SIMD functions withn=0using a tiny 8-byte dummy buffer. SVE functions usedo { } while (i < n)loops that execute once even withn=0, and MSan instruments predicated loads as full-width vector reads. Enlarged the buffer to 256 bytes to cover the widest SVE vector (2048 bits).Note
Medium Risk
Updates the
contrib/SimSIMDsubmodule, which changes low-level SIMD code paths on ARM and could impact correctness/performance if upstream behavior changed beyond the intended MSan fix.Overview
Fixes an ARM MSan false positive triggered by SVE predicated loads during SimSIMD capability probing.
This bumps the
contrib/SimSIMDdependency to an upstream change that enlarges the dummy probe buffer (from a tiny placeholder to a size that covers the widest SVE vectors), preventing out-of-bounds reads reported by MSan when probing withn=0.Written by Cursor Bugbot for commit ddbd9c3. This will update automatically on new commits. Configure here.