Commit ddbd9c3
Update SimSIMD to fix MSan false positive with SVE predicated loads
`simsimd_capabilities` probes SIMD functions with `n=0` using a tiny
8-byte dummy buffer. SVE functions use `do { } while (i < n)` loops
that execute once even with n=0, and MSan instruments predicated loads
as full-width vector reads. Enlarged the buffer to 256 bytes to cover
the widest SVE vector (2048 bits).
CI report: https://s3.amazonaws.com/clickhouse-test-reports/json.html?PR=98677&sha=a1b9d7f6170c510431fce962a869aa617d88d888&name_0=PR&name_1=Stress%20test%20%28arm_msan%29
Changelog category: CI Fix or Improvement
Changelog entry: Fix MSan false positive in SimSIMD SVE predicated loads.
Co-Authored-By: Claude Opus 4.6 <[email protected]>1 parent 0a82f6f commit ddbd9c3
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