Navaid Rizvi

Gautam Buddha University, School of ICT, Faculty Member

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School of the Art Institute of Chicago

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Ball State University

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University of Amsterdam

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University of Technology Sydney

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Kansas State University

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University of Cologne

Fausto Fraisopi

Aix-Marseille University

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Université Paris Est (Paris XII)

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The University of Western Australia

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Universiti Teknikal Malaysia Melaka

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Papers by Navaid Rizvi

Enabling highly-efficient OLED with solution-processed nanocrystalline copper phthalocyanine hole-injection/transport layer

Semiconductor Science and Technology, May 5, 2022

Design of a compact protrudent‐shaped ultra‐wideband multiple‐input‐multiple‐output/diversity antenna with band‐rejection capability

International Journal of RF and Microwave Computer-Aided Engineering, 2019

In this endeavor, a new multiple-input-multiple-output antenna with a sharp rejection at wireless... more In this endeavor, a new multiple-input-multiple-output antenna with a sharp rejection at wireless local area network (WLAN) band is designed and practically examined for portable wireless ultra-wideband applications. The intended diversity antenna possess a small size of 15 mm × 26 mm and two inverted L-strip are loaded over the conventional rectangular patch antenna to form protrudent-shaped radiator that acts as a radiating element. The sharp band-rejection capability at WLAN is established by incising the L-shaped slits at the decoupling structure. More than −21 dB isolation is accomplished for the complete working band (ie, 2.87-17 GHz). Degradation in the antenna efficiency at the center frequency of band rejection corroborates the good interference rejection capability. The working capabilities of the intended antenna are tested by using the isolation between the ports, total efficiency, gain, envelope correlation coefficient, radiation pattern, mean effective gain, and total active reflection coefficient.

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Implementation and Verification of Synchronous FIFO using System Verilog Verification Methodology

Journal of Communications Technology, Electronics and Computer Science, 2015

Developing complex nature of patterns & concurrency of Integrated Circuits has made conventional ... more Developing complex nature of patterns & concurrency of Integrated Circuits has made conventional coordinated test- benches an unworkable answer for testing. Nowadays, testing as a word has been substituted with check. Confirmation specialists need to guarantee what goes to the plant for assembling is an exact representation of the specification of configuration. Verification is the maximum time consuming stage in the whole design process, thus it has become a necessity to minimize the time required to encounter the confirmation necessities. The relentless growth in the complexity of the system, has led to the requirement of a more advanced, well organized and automated approach for creating verification environments. As the designs gets complex, the probability of occurrence of bugs increases. This nеcеssitatеd the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the synchronous FIFO design is v...

Design and Implementation of Low Power High Speed Viterbi Decoder

Procedia Engineering, 2012

This paper describes the design of Viterbi decoding algorithm and presents an implementation of t... more This paper describes the design of Viterbi decoding algorithm and presents an implementation of the decoder for the UWB MB_OFDM technology. The Viterbi algorithm is a maximum-likelihood algorithm for decoding of convolution codes. The algorithm tries to find a path of the trellis diagram, where the sequence of output symbols approximately matches the received sequence. To accomplish this task, it calculates for each path the path metric, which measures the distance to the received symbols sequence. BMU calculates the distance (metric) between the received noisy symbol and the output symbol of the state transition (branch). ACSU computes the accumulated metric associated with the sequence of transitions (path) to reach a state. When more then a path arrives to a state, ACSU selects the path with the lowest metric value, which is the survivor path. SMU stores the information that permits to trace back from a state to the previous one. This work also includes the design of ½ convolution encoder. The over all System will be designed using HDL language and simulation, synthesis and implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools. Finally the proposed system architecture performance speed, area, power and throughput.

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Parametric analysis of a hybrid 1-bit full adder in UDSM and CNTFET technology

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)

The basic arithmetic operation used in many VLSI circuits is addition, therefore reduction in pow... more The basic arithmetic operation used in many VLSI circuits is addition, therefore reduction in power dissipation of 1-bit adder cell will improve the performance of most of electronic devices. Carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have proposed CNTFETs for designing a 1-bit Hybrid full adder circuit, from which power, delay and power delay products are calculated. This paper also presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed and power consumption. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existing standard full adders and the proposed hybrid full adders [1] are designed and showed with better result comparison. This paper describes how the proposed hybrid full adders [1] are better in contrast to the standard full adders and also analyses how the standard full adders are not giving faithful results. The circuit was implemented using Cadence Virtuoso tools in 180, 90, 45nm and 32nm technology. We have tested these circuit for a supply of 1.8V for 180nm, 1.2V for 90nm, 1V for 45nm and 0.8V for 32nm CNTFET technology.

Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology

Journal of Electronic Design Technology Delay Analysis for VLSI Interconnect's Circuits

Smart Dust Wireless Sensor Networks (SDWSNs), which are

Smart Dust Wireless Sensor Networks (SDWSNs), which are the members of Wireless Sensor Network (W... more Smart Dust Wireless Sensor Networks (SDWSNs), which are the members of Wireless Sensor Network (WSN) family play a vital role as the requirements on communication node sizes and power consumption have become more stringent. Several low volume antennas have been designed and Low Noise Amplifier (LNA) and antenna co-designs have been devised to increase the level of design integration and reduce the receiver noise. In this paper we simulate two such antennas namely F Inverted Compact Antenna (FICA) and Planar Inverted F Antenna (PIFA) and compare their results to obtain the design with better performance.

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Greater Noida,India

The attributes of transistors such as length, width or oxide thickness are being scaled down when... more The attributes of transistors such as length, width or oxide thickness are being scaled down when integrated circuits are fabricated. This process variation becomes important at smaller process nodes as the variation becomes a larger percentage of the full length or width of the device. This transistor sizing causes measurable and predictable variance in the output performance of all circuits. In this work, PIFA antenna with LNA co-design has been implemented using two different technologies. First technology used, is the industry standard 180-nm CMOS-based technology family which includes both high-speed analog radio frequency (RF) CMOS and leading-edge silicon germanium (SiGe) BiCMOS technologies. Second technology used is 45-nm CMOS-based technology which implements transistors with dimensions of 120nm.The PIFA is designed to be used in low GHz Smart Dust Wireless Sensor Network, where no conventional Electrically Small Antennas (ESA) can be applied directly. The reflection co- e...

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Delay Analysis for VLSI Interconnectâ€™s Circuits

This research work has been comprised of three parts. The first part deals with the implementatio... more This research work has been comprised of three parts. The first part deals with the implementation and estimation for the delay of an inverter and study of the influence of the delay variations with the increased size of the inverter. In this modern era of VLSI integrated circuits, interconnect’s delay majorly influences the device delay. The second phase of the work emphasizes on the realization of the interconnect delay and interprets the change in interconnect delay with the change in the length of the interconnect. It has been observed that the interconnect delay varies quadratically with respect to its length. This causes the interconnect delay to become non-acceptable to be used as global interconnects, as they are quite large in length. The delay can further be reduced (linearized) by inserting inverters or buffer circuit in between the interconnectnet work. The next part is, to realize delay for the interconnect having buffer circuit. This, results in achieving the optimized...

Testability Techniques Used in Different Design Environment for Improving Fault Efficiency

The paper provides an overview of automatic creation of test patterns using different design for ... more The paper provides an overview of automatic creation of test patterns using different design for testability techniques (DFT). The main intent is to collect the data from specification, design and completely different synthesis environment and then applying various test conditions which aims at to reduce the time required for test case generation and also to relieve the designers from much tedious task. Increasing size and complexity of digital designs has made essential to address critical verification issues at the early stages of design cycle. Therefore, automated verification tools are necessary at higher levels of abstraction. In this context, we have discussed different design for testability techniques for automatically generating test sequence for functional circuits at register transfer level (RTL). These techniques have many advantages and disadvantages so a comparison based on few parameters essential in the circuit is shown to improve the fault efficiency. Experimental r...

Memristor Modelling for Common Source Amplifier Using 180 nm Technology

The objective of this research paper is on memristor modeling for common source amplifier circuit... more The objective of this research paper is on memristor modeling for common source amplifier circuit using cadence virtuoso tool at gpdk 180 nm technology. A memristor is the fourth element count after resistor, inductor and capacitor in fundamental electrical circuits assumption is proposed by Leon Chua, its characteristics is based on already occurred principles of voltages (V), current (I), flux (ᵩ) and charge (q). Ohm’s law states relation voltage to current is directly proportional by (V=IR), charge is directly proportional to voltage (q=CV), and relation between current to flux (φ=LI) and, as above equations represents that connection between flux (ᵩ) and the charge (q). Keywords: GPDK (generic process design kit), TEAM (ThrEshold adaptive memristor), memristors, SMCS (single memristor common source amplifier), DMCS (double memristor common source amplifier) Cite this Article Al Ayubi Herman, Rizvi Navaid Z, Mishra Piyush Kumar. Memristor Modelling for Common Source Amplifier usi...

Evaluation of transmission line and ring oscillator interconnect model for IC applications

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

The ability of an item to perform a required function under stated conditions for a specified per... more The ability of an item to perform a required function under stated conditions for a specified period of time. The main objective of this work is to analyze and estimate the reliability of a transmission line and thirteen stage ring oscillator as interconnects using GPDK 45 nm CMOS technology. As we know that reliability basically depends on HCI NBTI, PBTI and TDDB. Basically in this paper for the performance analysis we have analyzed the results in terms of transient response, delivered power by every component and noise analysis on different incident of time. In this work the reliability factors are done by comparing power, delay and output voltage after a specific amount of time.

Adiabatic logic: An alternative approach to low power application circuits

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

Today's major concerns in designing VLSI circuits have been the amount of power dissipated by... more Today's major concerns in designing VLSI circuits have been the amount of power dissipated by these circuits. The Adiabatic logic technique is becoming an answer to the problem of power dissipation. The term `Adiabatic' refers to the change of state that occurs without the loss or gain of heat. The adiabatic switching technique reduces the power dissipation during switching events. But, adiabatic circuits highly depend upon power clock and parameter variations. In this paper mux, one bit sum and carry adder are designed and simulated on cadence Virtuoso using 180nm technology. In an analysis PFAL is compared with conventional CMOS logic on the basis of frequency and supply voltage. The proposed technique shows the reduction of power dissipation as compared to the conventional CMOS design style. And results analysis accomplishes that adiabatic logic can be used for the implementation of relatively large, complex circuits that dissipate less energy than conventional CMOS designs.

Design of high PSRR folded cascode operational amplifier for LDO applications

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

This paper presents a novel CMOS folded cascode operational amplifier that leads to high PSRR and... more This paper presents a novel CMOS folded cascode operational amplifier that leads to high PSRR and provides gain nearly equal to that of a two stage op-amp. The proposed design is implemented in GPDK 0.18μm CMOS technology. This op-amp uses a folded cascode structure in the output stage combined with the differential amplifier having PMOS input transistors to achieve good input common mode range and lower flicker noise. It has an important feature that it allows the input common mode level close to supply voltage. The proposed topology improves the PSRR of op-amp which can be used for LDO applications. Simulations using Cadence under 1.8 V show a DC gain of 72.0404 dB and a phase margin of 62.4636 degree at a unity gain bandwidth of 13.33 MHz with the power consumption smaller than 0.13 mW along with a PSRR of 72.0966 dB. The layout of the design shows that the area acquired on the chip is approximately equal to 8897.27 μm2.

Performance analysis for full adder with Zipper logic

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

with the shrinking technology, new systems are designed that are miniature in size and perform fa... more with the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other logic the problem may arise with stored values. During pre-charge, the stored output can affect the circuit. In this paper, we propose Zipper logic for adder circuit so that it prevents any leakage due to stored charge. It also avoids the need of an additional inverter. The proposed adder is designed using cadence virtuoso at 45nm with the supply voltage of 1.2V. This improves the speed of operation by replacing inverter with N P block in alternate fashion.

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Class E power amplifier: Implementation and comparative analysis at 1.7GHz and 2.4GHz

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

The power amplifier is becoming most challenging modules to design in a wireless communication sy... more The power amplifier is becoming most challenging modules to design in a wireless communication system. Also, a wireless communication is demanding multi-band transmitter and receiver, so the design to get optimum efficiency and linearity in power amplifiers in multi-band applications becomes more and more challenging day by day. As such, a lot of work has been performed to design highly efficient and linear power amplifiers. The basic class E power amplifier and the cascode circuit of the class E power amplifier has been implemented and operated at two different frequencies (1.7GHz and 2.4GHz) to see the effect on the linearity parameter of PA. The voltage supply of 2.5V has been used and the input power of 12dBm. The simulation results clearly depict the linearity of the circuit with 50 ohm load.

Electronic model of human brain using verilog

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

Computers are man-made machines which work according to the given set of inputs and perform some ... more Computers are man-made machines which work according to the given set of inputs and perform some operation on the input to generate a new set of outputs. They can be programmed to perform huge and complex task yet they lack imagination and ability to understand things. On the hand human brain is a machine which can learn new tasks by process of acquiring knowledge and understanding through thought, experience and the senses. To make computer work or think like human, human brain modeling of machine is necessary. We need to know how human brain works. The basic component of human brain is neuron, which make us think and do smart things. Brains have billions of neurons and they communicate with each other using electrical impulse. These impulses are responsible for making brain think and to have a consciousness. This paper proposes such a model of a part of the brain.

CMOS low-noise amplifier for 2.4-GHz wireless receivers

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

This paper describes a 2.4GHz low noise amplifier (LNA) intended for use in receiver system. The ... more This paper describes a 2.4GHz low noise amplifier (LNA) intended for use in receiver system. The design has been done in 180nm technology using CMOS. The proposed LNA uses inductive degeneration technique. This amplifier provides a forward gain of 15.72dB with a low noise figure of .307dB while drawing 6.5mW from 1.8V supply voltage. The LNA uses a transformer as load. This paper presents a detailed analysis of the used design methodology and measured results.

Low power design of asynchronous SAR ADC

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

In this paper 8 bit SAR ADC with input voltage of 1.2V has been designed. The schematic diagram o... more In this paper 8 bit SAR ADC with input voltage of 1.2V has been designed. The schematic diagram of different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. Comparator was designed so that it remains in saturation for proper operation and was implemented using differential amplifier. The comparator is the main power consuming block, so most of our effort was focused on designing this block. In order to increase the precision, the R-2R ladder network was used for implementing DAC sub block. For driving ADC, asynchronous control logic was designed using Verilog coding, so there was no need for using a clock.