m300b Main PCB PDF
m300b Main PCB PDF
J J
I I
H H
G G
F F
E E
D D
C C
B B
A A
5 4 3 2 1
catalog
01 Cover sheet 43 GFX Switch
02 Block_Diagram 44 GPU Power Sequence
03 SMBUS & Reset Topology
D D
29 MiniCard1-WIFI
30 3G Card Connector & Powergoods
31 Camera & Blue Tooth
32
33
USB Port & LED & ME Holes
SATA Connector & Keyboard Connector
Notes:
34 KBC-IT8502E-NX Part Value Prefix : "@" means nopop
35 Small Board Connectors Net Value suffix : "#" means Low Active
36 Power_Charger & Battery Connector
37 Power_System +V5A-3.3A-1.5A
38 Power_+V1.5M_+V0.75M-1.8S
39 Power_+V1.05S & +V1.05S_VTT
A 40 Power_VCCSA A
Title <Title>
Size Sheet Rev
Cover Sheet
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 1 of 38
5 4 3 2 1
5 4 3 2 1
System Power
M300B/M300H BLOCK DIAGRAM TPS51125
SO DIMM1 TPS59641
DDR3L CH0
XDP
DDR3L CH1 SO DIMM2
R.G.B
CRT VGA
dGPU Power
HDMI
TPS51117
DDI0
HDMI
EDP DDI1
LCD
C C
SPI
SATA Bay Trail -M/D Soc Flash
Hard Disk DDR3L Power
TPS51216
SATA PCI-E PCI-E 0
ODD PCI-E LAN 25MHz
CLK_PCIE
USB3.0
USB3.0 DEVICE
S3/S4 Control
CLK_KBCPCI
KBC
and Discharge
USB2.0
USB2.0
TOUCH
FAN Flash KB PAD USB0 USB3.0
32.768KHz
USB1 WIFI
USB2 TOUCH
HDA HDA USB3 USB HUB
A A
Audio
Codec Lengda Technology Ltd.
5th floor,Block K,
Xiamen Exprot Processing Zone,
Haicang District,Xiamen,China,361026
Title <Title>
Size Sheet Rev
Block Diagram
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 2 of 38
5 4 3 2 1
5 4 3 2 1
SMBUS TOPOLOGY
CLK GEN
D SODIMM0
D
SMBCLK&SMBDATA
SODIMM1
PCH
MiniCard1
SML1CLK&SML1DATA
KBC
MiniCard2
SMB0
Battery
SMB1 SMB1
Thermal Sensor
SMB2 PECI
CPU Thermal
SMB3
GPU Thermal
C C
RESET TOPOLOGY
CPU
PLT_RST# BUF_PLT_RST#
Buffer HDD
B MiniCard1 B
MiniCard2
PCH GPU
KBC
ACZ_RST# LPC Port
Audio
DVD ROM
LAN
A A
Lengda Technology Ltd.
5th floor,Block K,
Xiamen Exprot Processing Zone,
Haicang District,Xiamen,China,361026
Title <Title>
Size Sheet Rev
SMBUS & RESET TOPOLOGY
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 3 of 38
5 4 3 2 1
BC BC
BB BB
BA BA
AZ
AY
POWER Delivery Architectural Block Diagram AZ
AY
AX AX
AW AW
Switch
AV
+V5.0S AV
AU AU
AT
DC-DC LDO AT
+V1.05S +V1.5S
AS AS
AR
Adapter AR
AP AP
AO AO
Switch
AN
+V1.8S AN
AM
DC-DC AM
NVDC(6V-12.6V)
Charger TPS51125 Switch
AL
APW8812 +V3.3A +V3.3S AL
AK AK
AJ AJ
Switch
AI +V1.0S AI
AH AH
BATTERY DC-DC
AG AG
TPS51117 Switch
AF
APW7141 +V1.0A +V1.0SX AF
AE AE
AD AD
AC Switch AC
+V1.35S
AB AB
AA AA
DC-DC
Z
TPS51216 Switch Z
X X
LDO
W +VSM_VTT W
V
DDR3L POWER Module V
U U
T T
S S
DC-DC
R R
TPS59641 +VCORE
Q Q
P P
O Driver O
TPS51604 +VGFX
N N
M M
CPU VCORE POWER Module(IMVP7)
L L
K K
J J
I I
H H
G G
F F
E
Lengda Technology Ltd. E
5th floor,Block K,
D Xiamen Exprot Processing Zone, D
Haicang District,Xiamen,China,361026
C C
Title <Title>
B B
Size Sheet Rev
Power_Trees
C Name A
A ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 5 of 38
A
5 4 3 2 1
5 4 3 2 1
U1B VLV_M_D
+V3.3A +VSM
+VSM
R34 R7
R6 100k 10k
4.7K ±1%
DDR3_VCCA_PWROK
DDR3L_VREF
3
S D
R9 2N7002LT1 2N7002LT1
4.7K ±1% 1 SOT95P240-3N 1 SOT95P240-3N
19 DDR3_VCCA_PWROK_3P3 G G
2
R10
1M
A A
Title <Title>
Size Sheet Rev
SOC DDR3L A & B
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 6 of 38
5 4 3 2 1
5 4 3 2 1
D D
+V1.8S
U1C VLV_M_D
R11
22 TMDS_DATAP2 AV3 AG3 eDP_TXP0 21 10k
AV2 DDI0_TXP_0 DDI1_TXP_0 AG1
22 TMDS_DATAN2 DDI0_TXN_0 DDI1_TXN_0 eDP_TXN0 21
22 TMDS_DATAP1 AT2 AF3 eDP_TXP1 21
+V1.8S AT3 DDI0_TXP_1 DDI1_TXP_1 AF2 DDI1_HPD
22 TMDS_DATAN1 DDI0_TXN_1 DDI1_TXN_1 eDP_TXN1 21
22 TMDS_DATAP0 AR3 AD3
AR1 DDI0_TXP_2 DDI1_TXP_2 AD2 +V1.8S
22 TMDS_DATAN0 DDI0_TXN_2 DDI1_TXN_2
3
22 TMDS_CLKP AP3 AC3 Q2
AP2 DDI0_TXP_3 DDI1_TXP_3 AC1 2N7002LT1
22 TMDS_CLKN
S D
R12 DDI0_TXN_3 DDI1_TXN_3 SOT95P240-3N
10k AL3 AK3 eDP_AUXP 21 1 DP_HPD 21
AL1 DDI0_AUXP DDI1_AUXP AK2 R13 G
DDI0_DDCDATA: DDI0_AUXN DDI1_AUXN eDP_AUXN 21
2
2.2k
0=DDI0 not detected DDI0_HPD D27 K30 DDI1_HPD
DDI0_HPD DDI1_HPD
1=DDI0 detected R14 10k POP = NA DDI1_DDCDATA: R15
C26 P30 DDI1_DATA DDI1_DATA 100k
22 HDMI_CTRLDATA DDI0_DDCDATA DDI1_DDCDATA 0=DDI1 not detected
3
POP = NA
AK13 AH14
R19 402 ±1% RC0402N AK12 DDI0_RCOMP RESERVED_AH14 AH13
AM14 DDI0_RCOMP_P RESERVED_AH13 AF14
AM13 RESERVED_AM14 RESERVED_AF14 AF13
AM3 RESERVED_AM13 RESERVED_AF13 AH3
C C
AM2 VSS_AM3 VSS_AH3 AH2
VSS_AM2 VSS_AH2
BA3
VGA_RED AY2
VGA_BLUE BA1
VGA_GREEN AW1
VGA_IREF AY3
VGA_IRTN
BD2
VGA_HSYNC BF2
VGA_VSYNC
BC1 R29 2.2k
VGA_DDCCLK BC2 R30 2.2k
VGA_DDCDATA
T2 T7
T3 RESERVED_T2 RESERVED_T7 T9
AB3 RESERVED_T3 RESERVED_T9 AB13
AB2 RESERVED_AB3 RESERVED_AB13 AB12
Y3 RESERVED_AB2 RESERVED_AB12 Y12
Y2 RESERVED_Y3 RESERVED_Y12 Y13
W3 RESERVED_Y2 RESERVED_Y13 V10
W1 RESERVED_W3 RESERVED_V10 V9
V2 RESERVED_W1 RESERVED_V9 T12
V3 RESERVED_V2 RESERVED_T12 T10
+V1.8S R3 RESERVED_V3 RESERVED_T10 V14
R1 RESERVED_R3 RESERVED_V14 V13
AD6 RESERVED_R1 RESERVED_V13 T14
AD4 RESERVED_AD6 RESERVED_T14 T13
AB9 RESERVED_AD4 RESERVED_T13 T6
R31 AB7 RESERVED_AB9 RESERVED_T6 T4
10k Y4 RESERVED_AB7 RESERVED_T4 P14
POP = NA Y6 RESERVED_Y4 RESERVED_P14
V4 RESERVED_Y6
V6 RESERVED_V4 K34
MDSI_DDCDATA: MDSI_DDCDATA A29 RESERVED_V6 RESERVED_K34 D32
0=DDI1 not detected C29 GPIO_S0_NC13 GPIO_S0_NC26 N32
GPIO_S0_NC14_C29 GPIO_S0_NC25
B
1=DDI1 detected AB14
RESERVED_AB14 GPIO_S0_NC24
J34
B
GPIO_S0 B30 K28
C30 GPIO_S0_NC12 GPIO_S0_NC23 F28
R32 RESERVED_C30 GPIO_S0_NC22 F32
10k GPIO_S0_NC21 D34
POP = NA GPIO_S0_NC20 J28
GPIO_S0_NC18 D28
GPIO_S0_NC17 M32
GPIO_S0_NC16 F34
3 OF 13 GPIO_S0_NC15
VLV_M_D
REV = 1.15
A A
Title <Title>
Size Sheet Rev
SOC DDI & VGA
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 7 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
RESERVED_AK9
AK9 R580 73.2 ±1% POP = NA +V1.0S
10k
POP = NA
10K 1=Normal Operation E
AK7
RESERVED_AK7
3
C24 Q100
PROCHOT H_PROCHOT# 26
SOT95P240-3N
S D
4 OF 13 2N7002LT1
VLV_M_D 1
G FLASH_TXE 26
REV = 1.15 R578 0
2
Co-Lay Q62
2 3
S D VR_HOT# 36
G
+V3.3S
2N7002LT1
D D
1
SOT95P240-3N
POP = NA
R579
1k
RC0402N
POP = NA
C C
B B
A Title <Title>
A
Size Sheet Rev
SOC SATA & PCIE & HDA
C Name A
ENGINEER: golden Date: Sunday, May 04, 2014 Sheet 8 of 38
5 4 3 2 1
+V3.3A +V1.8S
R56 R57
4.7K 100k
POP = NA
PMC_RSTBTN
D D
R58
5.6K
POP = NA
U1E VLV_M_D PMC_PWRBTN#
1
R129 51 POP = NA D14 A9
R131 51 POP = NA G12 TAP_TCK ILB_RTC_X2 B8 C13 100NF R69 X2 3 2
R582 51 POP = NA F14 TAP_TRST ILB_RTC_EXTPAD 10M Q13MC1461000200SM26BSPRC
R583 51 POP = NA F12 TAP_TMS RC0402N POP = NA X3
TAP_TDI
4
+V1.8A_SPI R584 51 POP = NA G16 32.768KHz
+V1.8A TAP_TDO
D18 OSC120P150X670-4L
F16 TAP_PRDY B24 R586 20±1%
+V1.8A_SPI TAP_PREQ SVID_ALERT SVID_ALERT# 36
AT34 A25 R587 16.9 ±1% C14 12pF CC0402N
RESERVED SVID_DATA SVID_DATA 36
C25 R588 0
SVID_CLK SVID_CLK 36
SPI_CS0# R70 22 C23
C21 PCU_SPI_CS_00
R72 SPI_SO R73 22 B22 PCU_SPI_CS_11 AU32
R71 3.3K SPI_SI R74 22 A21 PCU_SPI_MISO SIO_PWM_00 AT32
3.3K U3 SPI_CLK R75 22 C22 PCU_SPI_MOSI SIO_PWM_11
SPI_CS0# 1 8 VCC PCU_SPI_CLK
SPI_SO 2 CS# VCC 7 HD
R588 CRB是0ohm
WP# 3 DO(DQ1) NC(DQ3) 6 SPI_CLK B18
4 WP#(DQ2) CLK 5 SPI_SI 26 SOC_WAKE_SCI R80 10k B16 GPIO_S5_0 K24
VSS DI(DQ0) R110 10k C18 GPIO_S5_1 GPIO_S5_22 N24
EN25S64-104RIP R602 10k A17 GPIO_S5_2 GPIO_S5_23 M20 PM_RSMRST# R714 0 RC0402N
+V1.8A GPIO_S5_3 GPIO_S5_24 V1P8A_VR_PWRGD 34,35
C17 J18
C16 GPIO_S5_4 GPIO_S5_25 M18
25 PCIE_WIFI_WAKE# POP = NA
B14 GPIO_S5_5 GPIO_S5_26 K18
C15 GPIO_S5_6 GPIO_S5_27 K20
Co-Lay 26 SOC_EXTSMI# GPIO_S5_7 GPIO_S5_28 M22
GPIO_S5_29 M24
U75 GPIO_S5_30
SPI_CS0# 1 8 VCC C13
CS# VCC A13 GPIO_S5_8
SPI_SO 2 7 HD C19 GPIO_S5_9 AV32 +V1.8A
SO/SIO1 RESET#/SIO3 GPIO_S5_10 SIO_SPI_CS BA28
B
WP# 3 6 SPI_CLK SIO_SPI_MISO AY28 B
WP#/SIO2 SCLK R78 49.9 ±1% N26 SIO_SPI_MOSI AY30
4 5 SPI_SI GPIO_RCOMP SIO_SPI_CLK R83
GND SI/SIO0
E1
5 OF 13 2.2K
VLV_M_D
KH25U6439FZNI-10G REV = 1.15
E1
POP = NA
PMC_ACPRESENT
3
Q3
2N7002LT1
S D
Co-Lay SOT95P240-3N
+V1.8A_SPI 1
G AC_PRESENT 26
D36
2
P N AC_PRESENT:
BAT54WS-7-F Normal=H
+V1.8A
+V1.8A
+V3.3A S4/S5=L
R77 0 RC0603N
POP = NA
U5
1 8 C16 100NF
2 VIN1 VOUT1 7 R82 10k +V3.3S
R79 1k POP = NA 3 VIN2 VOUT2 6
4 ON CT 5 C21
E1
C19 U6
100NF 1 11
OE
Vinafix.com
PMC_SLP_S0IX 5 A3 B3 7
A ANPEC APL3526 P2P TI TPS22965 A4 B4 PM_SLP_S0IX# 19,22,26,33,37 A
TXB0104RUTR
6
SOC_FLASHEN 26
C530 C797
0.1u 0.1u
CC0402N CC0402N Lengda Technology Ltd.
POP = NA POP = NA
5th floor,Block K,
Xiamen Exprot Processing Zone,
Haicang District,Xiamen,China,361026
Title <Title>
Size Sheet Rev
SOC CLK & SPI & RTC & GPIOS
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 9 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J GPIO_S5_33:
1.floating = NON-CS Mode
J
U1F VLV_M_D
2.Connect to EC= CS Mode
G2 M10
GPIO_S5_31 RESERVED_M10 M9
RESERVED_M9
M3 P7
GPIO_S5_32 RESERVED_P7 P6
L1 RESERVED_P6
26 CS_WAKE R85 2.2K POP = NA K2 GPIO_S5_33
K3 GPIO_S5_34 M7
M2 GPIO_S5_35 RESERVED_M7 M12 R86 1.24K RC0402N
23 LAN_VDDEN_SOC N3 GPIO_S5_36 USB3_REXT0
21 TOUCHEN_SOC P2 GPIO_S5_37 P10
GPIO_S5_38 RESERVED_P10
I L3
GPIO_S5_39 RESERVED_P12
P12
M4
I
RESERVED_M4 M6
J3 RESERVED_M6
P3 GPIO_S5_40 D4
28 WIFI_VDDEN_SOC GPIO_S5_41 USB3_RXP0 USB3_RX0_P 29
H3 E3
GPIO_S5_42 USB3_RXN0 USB3_RX0_N 29
B12
GPIO_S5_43 K6
USB3_TXP0 USB3_TX0_P 29
K7
USB3_TXN0 USB3_TX0_N 29
M16
29 USB_PP0 USB_DP0
K16
29 USB_PN0 USB_DN0
Allocation USB Devices J14
28 USB_PP1 USB_DP1
G14
28 USB_PN1
USB3.0 Port1 USB_DN1
H USB0
21 USB_PP2
K12
J12 USB_DP2 +V3.3S
H
USB1 CAMERA 21 USB_PN2 USB_DN2 H8
K10 RESERVED_H8 H7 +V1.8S
USB2 Touch/TV CARD 17 USB_PP3
H10 USB_DP3 RESERVED_H7
17 USB_PN3 USB_DN3
USB3 USB HUB H5 +V1.8S
R729
10k
R87 1k±1% D10 RESERVED_H5 H4 RC0402N
ICLK_USB_TERMN_D10 RESERVED_H4
1
R88 1k±1% F10 Q102
R89 10k ICLK_USB_TERMN
+V1.8A
G
R90 10k DBG_UART3_TXD 2 3
C20 R91 S D
29 USB_OC0# USB_OC_00
B20 10k ±1% BSS138
USB_OC1# USB_OC_11 POP = NA
TP5 And TP6:
G C7 GPIO_S0_SC_55
BD12
BC12 Just For UART Debug G
R92 45.3 RC0402N D6 USB_RCOMPI GPIO_S0_SC_56 BD14 DBG_UART3_TXD +V3.3S
USB_RCOMPO GPIO_S0_SC_57 BC14
GPIO_S0_SC_58 BF14 +V1.8S
R93 0 POP = NA USB_PLL_MON M13 GPIO_S0_SC_59 BD16
USB_PLL_MON GPIO_S0_SC_60 BC16 DBG_UART3_RXD R94 R730
GPIO_S0_SC_61 10k ±1% 10k
POP = NA RC0402N
1
R95 0 HSIC0_DATA
POP = NA B4 BH12 SPKR 24 Q103
R96 0 HSIC0_STROBE
POP = NA B5 USB_HSIC0_DATA ILB_8254_SPKR
G
USB_HSIC0_STROBE DBG_UART3_RXD 2 3
S D
BSS138
R97 0 POP = NA E2 BH22
F R98 0 POP = NA D2 USB_HSIC1_DATA
USB_HSIC1_STROBE
SIO_I2C0_DATA
SIO_I2C0_CLK
BG23
F
R99 45.3 RC0402N A7
USB_HSIC_RCOMP BG24 SIO_I2C1_DATA R105 22 POP = NA
SIO_I2C1_DATA BH24 SIO_I2C1_CLK R107 22 POP = NA
SIO_I2C1_CLK
R100 49.9 ±1% BF18
26 LPC_AD[3..0] LPC_RCOMP
LPC_AD0 BH16 BG25
LPC_AD1 BJ17 ILB_LPC_AD_00 SIO_I2C2_DATA BJ25
LPC_AD2 BJ13 ILB_LPC_AD_11 SIO_I2C2_CLK
LPC_AD3 BG14 ILB_LPC_AD_22
BG17 ILB_LPC_AD_33 BG26
26 LPC_FRAME# R101 0 BG15 ILB_LPC_FRAME SIO_I2C3_DATA BH26
26 LPC_CLK_EC R102 0 POP = NA BH14 ILB_LPC_CLK_00 SIO_I2C3_CLK +V1.8S +V3.3S
BG16 ILB_LPC_CLK_11
E 26
26
LPC_CLKRUN#
LPC_SERIRQ
BG13 ILB_LPC_CLKRUN
ILB_LPC_SERIRQ SIO_I2C4_DATA
SIO_I2C4_CLK
BF27
BG27 E
C566 100NF POP = NAU74
1 8 C567 100NF POP = NA
BH28 2 VCCA VCCB 7
SIO_I2C5_DATA SOC_ICS5_DATA_TOUCH 21
SOC_SMB_DATA BG12 BG28 3 A1 B1 6
PCU_SMB_DATA SIO_I2C5_CLK SOC_ICS5_CLK_TOUCH 21
SOC_SMB_CLK BH10 4 A2 B2 5
+V1.8S BG11 PCU_SMB_CLK GND OE
PCU_SMB_ALERT BJ29 TXS0102DQER R683 10k POP = NA
SIO_I2C6_DATA BG29 R774 10k SON35P100-8N R684 10k POP = NA
SIO_I2C6_CLK +V1.8S +V3.3S
R106 2.2K POP = NA POP = NA
R108 2.2K POP = NA POP = NA
R109 2.2K POP = NA BH30 R775 +V1.8S R682 10k POP = NA
GPIO_S0_SC_092 BG30
GPIO_S0_SC_093 10k
D VLV_M_D
REV = 1.15
6 OF 13
POP = NA D
+V1.8S +V3.3S
C SON35P100-8N
R17 10k
R631 10k POP = NA +V3.3S
C
+V1.8S
B B
A Title <Title>
A
Size Sheet Rev
SOC USB & LPC & I2C
C Name A
ENGINEER: golden Date: Sunday, May 04, 2014 Sheet 10 of 38
10 9 8 7 6 5 4 3 2 1
J J
I I
+VSM
H +VSM
H
C22 C23 C24 C25 C26 C27 C28 C29
U1G VLV_M_D 2.2uF 2.2uF 2.2uF 2.2uF 0.1u 0.1u 0.1u 0.1u
CC0603N CC0603N CC0603N CC0603N POP = NA POP = NA
36 VCORE_VSNS P28 BD49
BB8 CORE_VCC_SENSE_P28 DRAM_VDD_S4_BD49 BD52
36 VGFX_VSNS UNCORE_VNN_SENSE DRAM_VDD_S4_BD52
36 VCORE_GSNS N28 BD53
+VSM CORE_VSS_SENSE_N28 DRAM_VDD_S4_BD53 BF44
DRAM_VDD_S4_BF44 BG51
DRAM_VDD_S4_BG51 BJ48
DRAM_VDD_S4_BJ48 C51
AD38 DRAM_VDD_S4_C51 D44
+VSM AF38 DRAM_VDD_S4_AD38 DRAM_VDD_S4_D44 F49
A48 DRAM_VDD_S4_AF38 DRAM_VDD_S4_F49 F52
G C30 C31
AK38
AM38
DRAM_VDD_S4
DRAM_VDD_S4_AK38
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
F53
H46
G
1uF 0.1u AV41 DRAM_VDD_S4_AM38 DRAM_VDD_S4_H46 M41
CC0402N CC0402N AV42 DRAM_VDD_S4_AV41 DRAM_VDD_S4_M41 M42 +VGFX +VGFX
+VCORE BB46 DRAM_VDD_S4_AV42 DRAM_VDD_S4_M42 V38
DRAM_VDD_S4_BB46 DRAM_VDD_S4_V38 Y38
DRAM_VDD_S4_Y38
AA27
AA29 CORE_VCC_S0IX_AA27 +VGFX
AA30 CORE_VCC_S0IX_AA29 C35 C36 C37
AC27 CORE_VCC_S0IX_AA30 C32 C33 C34 10uF 10uF 10uF
AC29 CORE_VCC_S0IX_AC27 AA24 1uF 1uF 1uF CC0603N CC0603N CC0603N
AC30 CORE_VCC_S0IX_AC29 UNCORE_VNN_S3_AA24 AC22
AD27 CORE_VCC_S0IX_AC30 UNCORE_VNN_S3_AC22 AC24
AD29 CORE_VCC_S0IX_AD27 UNCORE_VNN_S3_AC24 AD22
F +VCORE AD30
AF27
CORE_VCC_S0IX_AD29
CORE_VCC_S0IX_AD30
CORE_VCC_S0IX_AF27
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AD24
UNCORE_VNN_S3_AF22
AD24
AF22 F
AF29 AF24
AG27 CORE_VCC_S0IX_AF29 UNCORE_VNN_S3_AF24 AG22
AG29 CORE_VCC_S0IX_AG27 UNCORE_VNN_S3_AG22 AG24
AG30 CORE_VCC_S0IX_AG29 UNCORE_VNN_S3_AG24 AJ22
P26 CORE_VCC_S0IX_AG30 UNCORE_VNN_S3_AJ22 AJ24 +VGFX
P27 CORE_VCC_S0IX_P26 UNCORE_VNN_S3_AJ24 AK22
C38 C39 C40 C41 C42 U27 CORE_VCC_S0IX_P27 UNCORE_VNN_S3_AK22 AK24
10uF 4.7uF 4.7uF 2.2uF 2.2uF U29 CORE_VCC_S0IX_U27 UNCORE_VNN_S3_AK24 AK25
CC0603N CC0603N CC0603N CC0603N CC0603N V27 CORE_VCC_S0IX_U29 UNCORE_VNN_S3_AK25 AK27
V29 CORE_VCC_S0IX_V27 UNCORE_VNN_S3_AK27 AK29
V30 CORE_VCC_S0IX_V29 UNCORE_VNN_S3_AK29 AK30
Y27 CORE_VCC_S0IX_V30 UNCORE_VNN_S3_AK30 AK32 C43 C44 C45
Y29 CORE_VCC_S0IX_Y27 UNCORE_VNN_S3_AK32 AM22 0.1u 0.1u 0.1u
E Y30 CORE_VCC_S0IX_Y29
CORE_VCC_S0IX_Y30
UNCORE_VNN_S3_AM22 POP = NA POP = NA POP = NA
E
CORE_V1P05 AF30 AA22 VCC_SOIX
+VCORE TP_CORE_V1P05_S4 TP2_CORE_VCC_S0IX
7 OF 13
VLV_M_D
REV = 1.15
D D
C C
B B
A Title <Title>
A
Size Sheet Rev
SOC VCORE & VGFX & VDDR
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 11 of 38
5 4 3 2 1
+V1.0S +V1.0S +VSFR R111 R112 For HDA IO level R649 R650
0 0 0 0
RC0402N RC0402N +V1.8S POP = NA
POP = NA
For LPC IO level
C55 C49 C50
1uF 1uF 1uF
C56 C57
1uF C51 C52 C53 C54 1uF
1uF 1uF 1uF 1uF
+V1.0SX +V1.0SX_LC U1H VLV_M_D
V32 AD36
+V1.0SX_LC BJ6 SVID_V1P0_S3_V32 DRAM_V1P35_S0IX_F1_AD36 AM32
AD35 VGA_V1P0_S3_BJ6 HDA_LPE_V1P5V1P8_S3_AM32 AM30
C62 1uF AF35 DRAM_V1P0_S0IX_AD35 UNCORE_V1P8_S3_AM30 AN32
AF36 DRAM_V1P0_S0IX_AF35 UNCORE_V1P8_S3_AN32 AM27
C58 1uF AA36 DRAM_V1P0_S0IX_AF36 LPC_V1P8V3P3_S3_AM27 U24
AJ36 DRAM_V1P0_S0IX_AA36 UNCORE_V1P8_G3_U24 N18 +V3.3S
DRAM_V1P0_S0IX_AJ36 USB_V3P3_G3_N18 +V3.3A_SOC
AK35 P18 C59 1uF
+V1.0SX DRAM_V1P0_S0IX_AK35 USB_V3P3_G3_P18
+V1.0SX C61 1uF AK36 U38 C63 0.1u
+V1.0SX C60 1uF Y35 DRAM_V1P0_S0IX_AK36 UNCORE_V1P8_S3_U38 AN24
Y36 DRAM_V1P0_S0IX_Y35 VGA_V3P3_S3_AN24 V25 C506 0.1u CC0402N
AK19 DRAM_V1P0_S0IX_Y36 PCU_V1P8_G3_V25 N22
AK21 DDI_V1P0_S0IX_AK19 PCU_V3P3_G3_N22 AN27
DDI_V1P0_S0IX_AK21 SD3_V1P8V3P3_S3_AN27 +VSDIO
AJ18 AD16 C64 1uF POP = NA
AM16 DDI_V1P0_S0IX_AJ18 VSS_AD16 AD18 R115 0 +V1.0A
+V1.0SX DDI_V1P0_S0IX_AM16 VSS_AD18
+V1.0A U22 V18
C66 C67 C65 1uF V22 UNCORE_V1P0_G3_U22 USB_HSIC_V1P2_G3_V18 AA18
UNCORE_V1P0_G3_V22 UNCORE_V1P8_G3_AA18 +V1.8A
1uF 1uF C69 C68 1uF AN29 P22 Co-Lay
VIS_V1P0_S0IX_AN29 RTC_VCC_P22 +V3.3A_RTC
CC0603N 1uF AN30 N20 C597 1uF R293 0
AF16 VIS_V1P0_S0IX_AN30 USB_V1P8_G3_N20 U25 C71
+V1.0S UNCORE_V1P0_S3_AF16 PMU_V1P8_G3_U25
C70 1uF AF18 AF33 1uF
Y18 UNCORE_V1P0_S3_AF18 CORE_V1P05_S3_AF33 AG33
C +V1.0S
C72 0.01uF G1 UNCORE_V1P0_S3_Y18 CORE_V1P05_S3_AG33 AG35 C73 C74
+V1.2A for USB HSIC C
U73
Co-Lay C548
C97 C98 5 10uF
1uF 1uF VIN 1 CC0603N
R358 0 POP = NA 4 VOUT POP = NA
C560 SS
+V1.35S +V1.35_CRT 10uF C561 3 2
CC0603N 1uF C549 EN/ENBGND
POP = NA 0.01uF APL3512A/B
CC0402N SOT95P280-5N
R119 0 RC0603N
POP = NA
C99 C100
10uF 22uF
CC0603N CC0805N
26 3.3ASOC_ONOFF
A A
Title <Title>
Size Sheet Rev
SOC POWERS
C Name A
ENGINEER: golden Date: Tuesday, May 06, 2014 Sheet 12 of 38
5 4 3 2 1
5 4 3 2 1
BF30 E8 K9 U3
BF36 VSS211 VSS246 F19 L13 VSS281 VSS316 U30
BF4 VSS212 VSS247 F2 L19 VSS282 VSS317 U32
BG31 VSS213 VSS248 F24 L27 VSS283 VSS318 U40
BG34 VSS214 VSS249 F27 L35 VSS284 VSS319 U42
BG39 VSS215 VSS250 F30 M19 VSS285 VSS320 U43
BG42 VSS216 VSS251 F35 M26 VSS286 VSS321 U45
BG45 VSS217 VSS252 F5 M27 VSS287 VSS322 U46
BG49 VSS218 VSS253 F7 M34 VSS288 VSS323 U48
BJ11 VSS219 VSS254 G10 M35 VSS289 VSS324 U49
BJ15 VSS220 VSS255 G20 M38 VSS290 VSS325 U5
BJ19 VSS221 VSS256 G22 M47 VSS291 VSS326 U51
BJ23 VSS222 VSS257 G26 M51 VSS292 VSS327 U53
BJ27 VSS223 VSS258 G28 N1 VSS293 VSS328 U6
BJ31 VSS224 VSS259 G32 N16 VSS294 VSS329 U8
BJ35 VSS225 VSS260 G34 N38 VSS295 VSS330 U9
BJ39 VSS226 VSS261 G42 N51 VSS296 VSS331 V12
B
BJ43 VSS227 VSS262 H19 P13 VSS297 VSS332 V16 B
BJ47 VSS228 VSS263 H27 P16 VSS298 VSS333 V19
BJ7 VSS229 VSS264 H35 P19 VSS299 VSS334 V21
C14 VSS230 VSS265 J1 P20 VSS300 VSS335 V35
C31 VSS231 VSS266 J16 P24 VSS301 VSS336 V40
C34 VSS232 VSS267 J19 P32 VSS302 VSS337 V44
C39 VSS233 VSS268 J22 P35 VSS303 VSS338 V51
C42 VSS234 VSS269 J27 P38 VSS304 VSS339 V7
C45 VSS235 VSS270 J32 P4 VSS305 VSS340 Y10
C49 VSS236 VSS271 J35 P47 VSS306 VSS341 Y14
D12 VSS237 VSS272 J40 P52 VSS307 VSS342 Y16
D16 VSS238 VSS273 J53 P9 VSS308 VSS343 Y21
D24 VSS239 VSS274 K14 T40 VSS309 VSS344 Y25
D30 VSS240 VSS275 K22 U1 VSS310 VSS345 Y33
D36 VSS241 VSS276 K32 U11 VSS311 VSS346 Y41
D38 VSS242 VSS277 K36 U12 VSS312 VSS347 Y44
E19 VSS243 VSS278 K4 U14 VSS313 VSS348 Y7
E35 VSS244 VSS279 K50 U21 VSS314 VSS349 Y9
VSS245 VSS280 VSS315 VSS350
12 OF 13 13 OF 13
VLV_M_D VLV_M_D
REV = 1.15 REV = 1.15
A A
Title <Title>
Size Sheet Rev
SOC VSS
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 13 of 38
5 4 3 2 1
5 4 3 2 1
DDR3 SODIMM0
Layout Note:
Place the 0-Ω resistors close to SO-DIMM connector.
The overall routing length for both DIMM_VREF traces should be <= 5000 mils (127 mm).
Avoid changing reference plane during the entire routing length. If reference plane has to be changed
during the transition to 0-Ω resistors, then GND stitching vias are needed next to resistor pads.
Place GND stitching vias within 100 mils (2.54 mm) of DIMM_VREF traces close to SO-DIMM connector.
D D
CN3A
6 M_A_A[15..0] M_A_DQ[63..0] 6
M_A_A0 98 5 M_A_DQ0
M_A_A1 97 A0 DQ0 7 M_A_DQ1
M_A_A2 96 A1 DQ1 15 M_A_DQ2 +VSM
M_A_A3 95 A2 DQ2 17 M_A_DQ3
M_A_A4 92 A3 DQ3 4 M_A_DQ4 CN3B
M_A_A5 91 A4 DQ4 6 M_A_DQ5 75 44
M_A_A6 90 A5 DQ5 16 M_A_DQ6 76 VDD1 VSS16 48
M_A_A7 86 A6 DQ6 18 M_A_DQ7 81 VDD2 VSS17 49
M_A_A8 89 A7 DQ7 21 M_A_DQ8 82 VDD3 VSS18 54
M_A_A9 85 A8 DQ8 23 M_A_DQ9 87 VDD4 VSS19 55
M_A_A10 107 A9 DQ9 33 M_A_DQ10 88 VDD5 VSS20 60
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 93 VDD6 VSS21 61
M_A_A12 83 A11 DQ11 22 M_A_DQ12 94 VDD7 VSS22 65
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 99 VDD8 VSS23 66
M_A_A14 80 A13 DQ13 34 M_A_DQ14 100 VDD9 VSS24 71
M_A_A15 78 A14 DQ14 36 M_A_DQ15 105 VDD10 VSS25 72
A15 DQ15 39 M_A_DQ16 106 VDD11 VSS26 127
109 DQ16 41 M_A_DQ17 +V3.3S 111 VDD12 VSS27 128
6 M_A_BS0 BA0 DQ17 VDD13 VSS28
Note: 6 M_A_BS1
108
BA1 DQ18
51 M_A_DQ18 112
VDD14 VSS29
133
If SA0_DIM0 = 0, SA1_DIM0 = 0 79 53 M_A_DQ19 117 134
6 M_A_BS2 BA2 DQ19 VDD15 VSS30
M_CS#0 114 40 M_A_DQ20 118 138
SO-DIMMA SPD Address is 0xA0 6 M_CS#0
M_CS#1 121 S0# DQ20 42 M_A_DQ21 123 VDD16 VSS31 139
SO-DIMMA TS Address is 0x30 6 M_CS#1
M_CLK_DDR0 101 S1# DQ21 50 M_A_DQ22 C101 C102 124 VDD17 VSS32 144
If SA0_DIM0 = 1, SA1_DIM0 = 0 6 M_CLK_DDR0 CK0 DQ22 VDD18 VSS33
M_CLK_DDR#0 103 52 M_A_DQ23 0.1u 0.1u 145
6 M_CLK_DDR#0 CK0# DQ23 +VSM VSS34
SO-DIMMA SPD Address is 0xA2 6 M_CLK_DDR1
M_CLK_DDR1 102
CK1 DQ24
57 M_A_DQ24 199
VDDSPD VSS35
150
SO-DIMMA TS Address is 0x32 M_CLK_DDR#1 104 59 M_A_DQ25 151
6 M_CLK_DDR#1 CK1# DQ25 VSS36
M_CKE0 73 67 M_A_DQ26 77 155
6 M_CKE0 CKE0 DQ26 NC1 VSS37
M_CKE1 74 69 M_A_DQ27 122 156
6 M_CKE1 CKE1 DQ27 NC2 VSS38
C M_A_CAS# 115 56 M_A_DQ28 125 161 C
6 M_A_CAS# CAS# DQ28 NCTEST VSS39
M_A_RAS# 110 58 M_A_DQ29 R120 162
6 M_A_RAS# RAS# DQ29 VSS40
+V3.3S R121 10k RC0402N POP = NA M_A_WE# 113 68 M_A_DQ30 1k±1% R581 0 POP = NA 198 167
6 M_A_WE# WE# DQ30 26 DDR3L_EVENT EVENT# VSS41
R122 10k RC0402N SA0_DIM0 197 70 M_A_DQ31 30 168
SA0 DQ31 6 DDR3L_DRAMRST# RESET# VSS42
R123 10k RC0402N SA1_DIM0 201 129 M_A_DQ32 172
SMB_CLK_S2 202 SA1 DQ32 131 M_A_DQ33 VREF_DQ0 1 VSS43 173
10,23,25 SMB_CLK_S2 SCL DQ33 VREF_DQ VSS44
SMB_DATA_S2 200 141 M_A_DQ34 126 178
10,23,25 SMB_DATA_S2 SDA DQ34 VREF_CA VSS45
143 M_A_DQ35 179
M_ODT0 116 DQ35 130 M_A_DQ36 C103 C104 2 VSS46 184
6 M_ODT0 ODT0 DQ36 VSS1 VSS47
M_ODT1 120 132 M_A_DQ37 R124 0.1u 0.1u 3 185
6 M_ODT1 ODT1 DQ37 VSS2 VSS48
140 M_A_DQ38 1k±1% POP = NA 8 189
6 M_A_DM[7..0] DQ38 VSS3 VSS49
M_A_DM0 11 142 M_A_DQ39 9 190
M_A_DM1 28 DM0 DQ39 147 M_A_DQ40 13 VSS4 VSS50 195
M_A_DM2 46 DM1 DQ40 149 M_A_DQ41 14 VSS5 VSS51 196
M_A_DM3 63 DM2 DQ41 157 M_A_DQ42 19 VSS6 VSS52 +VSM_VTT
M_A_DM4 136 DM3 DQ42 159 M_A_DQ43 +VSM 20 VSS7
M_A_DM5 153 DM4 DQ43 146 M_A_DQ44 25 VSS8
M_A_DM6 170 DM5 DQ44 148 M_A_DQ45 26 VSS9 203
M_A_DM7 187 DM6 DQ45 158 M_A_DQ46 31 VSS10 VTT1 204
DM7 DQ46 160 M_A_DQ47 32 VSS11 VTT2
6 M_A_DQS[7..0] DQ47 VSS12
M_A_DQS0 12 163 M_A_DQ48 R125 37
M_A_DQS1 29 DQS0 DQ48 165 M_A_DQ49 1k±1% 38 VSS13 E1 C105
M_A_DQS2 47 DQS1 DQ49 175 M_A_DQ50 43 VSS14 E1 E2 10uF
M_A_DQS3 64 DQS2 DQ50 177 M_A_DQ51 VSS15 E2 CC0603N
M_A_DQS4 137 DQS3 DQ51 164 M_A_DQ52 VREF_CA0
M_A_DQS5 154 DQS4 DQ52 166 M_A_DQ53
M_A_DQS6 171 DQS5 DQ53 174 M_A_DQ54 0705A1BA52E/0705A1BE52E
M_A_DQS7 188 DQS6 DQ54 176 M_A_DQ55 C106 C107
6 M_A_DQS#[7..0] DQS7 DQ55
M_A_DQS#0 10 181 M_A_DQ56 R126 0.1u 0.1u
M_A_DQS#1 27 DQS#0 DQ56 183 M_A_DQ57 1k±1% POP = NA
M_A_DQS#2 45 DQS#1 DQ57 191 M_A_DQ58
M_A_DQS#3 62 DQS#2 DQ58 193 M_A_DQ59
M_A_DQS#4 135 DQS#3 DQ59 180 M_A_DQ60
M_A_DQS#5 152 DQS#4 DQ60 182 M_A_DQ61
M_A_DQS#6 169 DQS#5 DQ61 192 M_A_DQ62
M_A_DQS#7 186 DQS#6 DQ62 194 M_A_DQ63
DQS#7 DQ63
B +VSM B
0705A1BA52E/0705A1BE52E
+VSM_VTT
1
CP1 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119
+ 330uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 1uF 1uF 1uF 1uF
CCP7343N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0402N CC0402N CC0402N CC0402N
POP = NA POP = NA POP = NA POP = NA POP = NA POP = NA POP = NA
2
Note:
Note: Place close to SODIMM Place Next to the SODIMM
+VSM
A A
Title <Title>
Size Sheet Rev
DDR3L_SODIMM0
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 14 of 38
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title <Title>
Size Sheet Rev
CPU FAN & Thermal Sensor
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 15 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
I I
H H
G G
F F
E E
D D
C C
B B
A Title <Title>
A
Size Sheet Rev
BLANK
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 16 of 38
5 4 3 2 1
D D
GL850_AVDD GL850_AVDD
+V3.3S 3.3V_IN
GL850_AVDD
C575 C576
1uF 0.1u
CC0402N CC0402N
+V5S
X7
GL850G_X1 2 1 GL850G_X2
C580
20PF R696
C579 OSC-2 CC0402N 499K ±1%
C C
20PF
CC0402N
+V5S PSELF
Note:
R692 As close to GL850G R697
Note:
10k 4.7K PSELF=0 GL850G is bus powered
RC0402N POP = NA PSELF=1 GL850G is self powered
GL850G_RST#
R698 C578
47K 1uF
RC0402N CC0402N
B B
+V3.3S +V5S
CAM_ON
26 CAM_ON
USE APL3512A High Enable
A R478 A
10k
RC0402N
Title <Title>
Size Sheet Rev
USB HUB
C Name A
ENGINEER: golden Date: Tuesday, May 06, 2014 Sheet 17 of 38
5 4 3 2 1
5 4 3 2 1
D D
+V5A
+V1.05S +V1.5S
R562
100k
SLP_S3# DISCHARGE CIRCUIT RC0402N R567 R565
470 470
DESIGNED FOR ~100ms RC0402N RC0402N
DISCHARGE ON ALL S3
RAILS.
3
Q48 Q53 Q51
S D
S D
S D
2N7002LT1 R574 2N7002LT1 2N7002LT1
1 1M 1 1
9,22,26,33,36 PM_SLP_S3# G G G
RC0402N
2
S3_DISCHARGE 33,34,35,37
C539
100NF
POP = NA
C C
VREG5
R569 R570 R571 R572
470 470 470 470
RC0402N RC0402N RC0402N RC0402N
POP = NA POP = NA POP = NA POP = NA
POP = NA R662
3
100k
RC0402N Q55 Q56 Q57 Q58
S D
S D
S D
S D
2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1
ALW_DISCHARGE 1 POP = NA1 POP = NA1 POP = NA1 POP = NA
G
2 G G G
2
3
Q85
S D
2N7002LT1 R663
1 1M
19,32 VR_ALW_EN G RC0402N
ALW_DISCHARGE 34,35
2
POP = NA
B POP = NA B
A A
Title <Title>
Size Sheet Rev
Powers Discharge
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 18 of 38
5 4 3 2 1
5 4 3 2 1
D D
+V5S
R386 +V3.3A
10k
RC0402N
U36
BUF_PLT_RST# 1 5 C321 0.1u CC0402N
A VCC
ALL_SX_S_PWRGD 2
B
3 4
GND Y ALL_SYS_PWRGD 26
SN74AHC1G32
R679 0 SOT65P210-5N
+V3.3A
U38
1 5 C329 0.1u +V3.3A
A VCC
2
9,19,22,26,33,37 PM_SLP_S0IX# B U40
3 4 VCCAPWROK_AND 1 5 C332 0.1u
GND Y A VCC
C SN74AHC1G08 2 C
B
3 4 DDR3_VCCA_PWROK_3P3 6
GND Y
SN74AHC1G08
+V3.3A
U37
1 5 C326 0.1u +V3.3A
9,19,22,26,33,37 PM_SLP_S0IX# A VCC
ALL_SYS_PWRGD 2
B U39
3 4 DELAY_ALL_SYS_PWRGD 1 5 C331 0.1u
GND Y A VCC
SN74AHC1G08 2
9,23,25,26 BUF_PLT_RST# B
POP = NA
3 4 R387 100k
GND Y CORE_PWROK 9
R8 0 POP = NA
SN74AHC1G32
Co-Lay SOT65P210-5N
R388 0
26 EC_DELAY_ALL_SYS_PWRGD
R713 0 POP = NA
B B
VREG3
U71
1 5 C540 0.1u CC0402N
31 ACOK A VCC
2
26,30 SMC_SHUTDOWN# B
3 4
GND Y VR_ALW_EN 18,32
SN74AHC1G32
SOT65P210-5N
POP = NA
A A
Title <Title>
Size Sheet Rev
Platfom PWRGOOD
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 19 of 38
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title <Title>
Size Sheet Rev
BLANK
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 20 of 38
5 4 3 2 1
5 4 3 2 1
E1
E2
E1
E2
+V3.3S
R149 0
10 TOUCHEN_SOC
R766
R592 0 POP = NA 10k
26 TP_EN_EC
RC0402N
Co-Lay
+V3.3S
+V3.3S
R616
+V_DC +V5S 10K
+V3.3S RC0402N
U61
5
R735
Co-Lay POP = NACo-Lay eDP_BKLEN_3P3 1
0 R736
Co-Lay 10UH R617 4EDP_BKLEN_OUT R720 0 POP = NA EC_BLEN 26
RC0805N 0 R157 0 RC0805N L1 1 2 LC4340N D29 P N 1N5819 +V_LED_A 100k 26 BLCTL_EC 2
3
POP = NA RC0805N RC0402N For 11.6 EDP
POP = NA
sod5225n Q17 SN74LVC1G08DCKR
D
POP = NA POP = NA
3
Q6 4.7uH D4 2N7002LT1 R719
POP = NA
VIN_LCD 2 3 L2 1 2 LC5757N P N 1 0
S D G
S
2
G
3
C301 C165 C163 SOT95P280-3N SOD2818N
1
S D
POP = NA CC0603N CC0603N CC0603N C166 4.7uF 4.7uF Q16
0.033uF CC1206N CC1206N 7 eDP_BKLEN 1 BSS138
POP = NA POP = NA G
CC0603N
2
POP = NA POP = NA
B POP = NA B
R158 4.7UF/ 1206 /50V耐压 R163
EDP
3K+/-1 1M
RC0603N
POP = NA
C170
R160 1uF
0 CC0402N
25
24
23
22
21
20
19
RC0402N U11
POP = NA
POP = NA R167
COMP
FAULT
25
LX1
LX2
VDC
VIN
1M
RC0402N
POP = NA
R164 100k EDP_BKLEN_OUT 1 18
EN PGND1 POP = NA
2
3 NC APW7227 PGND2
17
16
VOUT = (1+RUPPER/RLOWER) x 1.2V.
C173 0.1u
4 FPWM OVP 15 IINA0
POP = NA 5 DCI IIN0 14 IINA1
6 GND IIN1 13 IINA2
R172 C174 PWMI IIN2 R173
0 220NF 33K+/-1
RC0603N CC0402N RC0603N
RSET
IIN7
IIN6
IIN5
IIN4
IIN3
POP = NA
POP = NA
POP = NA
7
8
9
10
11
12
5th floor,Block K,
S D
R178 <Title>
1M Title
Size Sheet Rev
LCD CONN & VLED
C Name A
ENGINEER: golden Date: Sunday, May 04, 2014 Sheet 21 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
+V3.3S
15
14
13
U14
DO-VCC1
D1- NC
D2- VCC
TPD8S009
GND11
I I
GND2
GND5
GND8
POP = NA
DO+
D1+
D2+
D3+
For HDMI ESD
D3-
7 TMDS_DATAP2 C175 0.1u CC0402N OUT_D2+
7 TMDS_DATAN2 C176 0.1u CC0402N OUT_D2- Place as close to the HDMI CONN as possible
1
2
3
4
5
6
7
8
9
10
11
12
7 TMDS_DATAP1 C177 0.1u CC0402N OUT_D1+
7 TMDS_DATAN1 C178 0.1u CC0402N OUT_D1-
POP = NA
Q8 F2 2 1 f1206n P N
S D
SOT95P240-3N
R502 0 1 2N7002LT1 U15 GND_HDMI
9,19,26,33,37 PM_SLP_S0IX# G BAT54WS-7-F
C183
VOUT
2 1920x 1200 @ 60 Hz using HDMI
2
+V1.8S +V5S_HDMI
+V3.3S
E +V3.3S
E
R202 R203 R204 R205
2
2.2K 2.2K 2.2K 2.2K
RC0402N RC0402N RC0402N RC0402N D6
SOT95P280-3N
1
HPD_CONN 3 POP = NA
Q9 7 HDMI_HPD
G
2 3 2N7002LT1 SCL_CONN
7 HDMI_CTRLCLK S D SOT95P240-3N
1
1
Q10
G
C C
B B
A Title <Title>
A
Size Sheet Rev
HDMI Port
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 22 of 38
5 4 3 2 1
X4
XTAL1 2 1 XTAL2
One pin dual lay
R207 0 RC0603N POP = NA +V3.3S C186 20PF CC0402N
25MHz
+V3.3A
Co-Lay C187 20PF CC0402N
R206 0 RC0603N VDD33 VDD33
D
5
U16
C190 C191 C192 C193 C194 C195 C196 R314 value should be 2.49K D
VIN
R212 0 RC0402N POP = 4
NA VOUT
1
10uF
0.1u
CC0402N
0.1u
CC0402N
0.1u 0.1u
CC0402N CC0402N
0.1u
CC0402N
0.1u
CC0402N
(1%) for all application.
SS CC0603N R209
3 2 2.49K+/-1
C511 C188 EN/ENBGND RC0603N
10uF 1uF APL3512A/B C242-C245,C318 are for 8105E VDD33 pins--27,39,42,47,48
CC0603N CC0603N SOT95P280-5N C242-C245 C318 C301 are for 8111E VDD33 pins-- 27,39,42,47,48,12
POP = NAPOP = NA C510
100NF POP = NA R210 10k RC0402N
CC0402N EEDI
POP = NA R211 0 RC0603N AVDD33_REG
R213 10k RC0402N
C197 C198 EECS
VDD33
VDD33
VDD10
VDD33
VDD10
VDD33
4.7uF 0.1u
XTAL2
XTAL1
RSET
EESK
GPO
CC0603N Remove
CC0402N For Disable
R208 0 POP = NA Switch Regulator
LAN_VDDEN_SOC 10
R593 0 POP = NA LAN_VDDEN_EC 26 (Accept External 1.05V
Power Supply ) U17
48
47
46
45
44
43
42
41
40
39
38
37
R765 Co-Lay
VDD33
10k E1
AVDD33B
AVDD33A
AVDD10A
LED1/EESK
RSET
CKXTAL2
CKXTAL1
AVDD33
DVDD10(NC)
LED0
DVDD3
GPO/SMBALERT
RC0402N EPAD
POP = NA R214 0
RC0603N
R312 For Enable Switch Regulator.
R315 For Disable Switch
MDI0+ 1 36 REGOUT Regulator.
MDI0- 2 MDIP0 REGOUT 35 AVDD33_REG
VDD10 3 MDIN0 VDDREGA 34 AVDD33_REG R215 0
MDI1+ 4 AVDD10 VDDREG 33 ENSWREG
MDI1- 5 MDIP1 ENSWREG 32 EEDI
VDD10 6 MDIN1 EEDI 31 EEDO RC0603N POP = NA
MDI2+ 7 AVDD10(NC) LED3/EEDO 30 EECS
MDI2- 8 MDIP2(NC) EECS 29 VDD10
VDD10 9 MDIN2(NC) DVDD10A 28 LANWAKEB R216 0 RC0402N +V3.3S
MDI3+ 10 AVDD10A(NC) LANWAKEB 27 VDD33 PCIE_LAN_WAKE# 9
MDI3- 11 MDIP3(NC) DVDD33 26 ISOLATEB R217 1k RC0402N
VDD33 12 MDIN3(NC) ISOLATEB 25 PERSTB R218 0 RC0402N
C BUF_PLT_RST# 9,19,25,26 C
AVDD33(NC) PERSTB
SMBDATA(NC)
SMBCLK(NC)
* C256-C259,C260,C320,C321 are for 8111E VDD10 pins-- 3, 13, 29,45,6,9,41. R219
REFCLK_N
REFCLK_P
15K
CLKREQB
DVDD10
EVDD10
RC0402N
HSON
HSOP
* C256-C259 are for 8105E VDD10 pins--3, 13, 29, 45
HSIN
HSIP
GND
2.2uH
REGOUT 1 2 VDD10
13
14
SMBDATA 15
16
17
18
19
20
21
22
23
GND 24
L4
C201 C202 C203 C204 C205 C206 C207 VDD33
C199 C200 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
SMBCLK
EVDD10
4.7uF 0.1u CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N
VDD10
CC0603N CC0402N
1
Q64
Co-Lay
G
2 3 HSON C208 0.1u CC0402N
8 CLK_LAN_OE# S D HSOP C209 0.1u CC0402N PCIE_RXN0_LAN 8
PCIE_RXP0_LAN 8
* C250 and C251 are for U13 VDD10 pin 21 2N7002LT1 REFCLK_N
REFCLK_P
CLK_PCIE_LAN_N 9
Remove For Disable Switch Regulator R634 0 POP = NA
CLK_PCIE_LAN_P 9
HSIN
(Accept External 1.05V Power Supply ) R220 0 RC0603N EVDD10 HSIP
PCIE_TXN0_LAN 8
PCIE_TXP0_LAN 8
C210 C211
0.1u
1uF CC0402N SMBCLK R632 0 POP = NA SMB_CLK_S2 10,14,25
CC0402N SMBDATA R633 0 POP = NA SMB_DATA_S2 10,14,25
Function
R221 0 RC0603N
3 330mA 4
B3 GND
B B
POP = NA R223 10k SMBDATA
2 1
FIL1
B2 UNB
POP = NA
R222 0 RC0603N
R224 0 RC0603N
2B2 FIL2 UNB 1
Title <Title>
Size Sheet Rev
PCIE-GIGA LAN
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 23 of 38
5 4 3 2 1
8 7 6 5 4 3 2 1
+V5S
+V5_AVDD
+V5_PVDD FB5
+V5S
FB6
+V1.5S +V1.5S_AUDIO
180ohm
C224 FB0603N
180ohm 1uF R240 0
C226 FB0603N CC0603N
1uF POP = NA
CC0603N C229 100NF CC0402N POP = NA
POP = NA
D D
GND
AC_VREF C230 4.7uF CC0603N AGND
C231 C232 100NF CC0402N
+V3.3S_AUDIO +V1.5S_AUDIO 2.2uF
+V3.3S_AUDIO CC0603N
GND
R249
1k
MIC1R-VREFO
MIC1L-VREFO
MIC2-VREFO AUD_MIC_IN
MIC2-VREFO
FB8 FB9 C233 C234 +V5_AVDD
180ohm 180ohm 10uF 100NF C235 RC0402N
+V3.3S FB0603N CC0603N CC0402N 10uF
+V3.3S_AUDIO POP = NA CC0603N AUD_MIC_IN_R C236 4.7uF R242 1K RC0603N
FB0603N POP = NA AGND
FB7
C239 C240 AUD_MIC_IN_L C237 4.7uF R245 1K RC0603N
100NF
CC0402N 10uF
C243 C244 U23 CC0805N
36
35
34
33
32
31
30
29
28
27
26
25
180ohm 100NF 10UF C245 ALC282 POP = NA
C241 FB0603N CC0402N CC0603N 2.2uF
MIC1-VREFO-L
AVDD1
AVSS1
CPVDD
CBN
CPVEE
HPOUT-R(PORT-I-R)
HPOUT-L(PORT-I-L)
MIC1-VREFO-R
MIC2-VREFO
VREF
LDO1-CAP
1uF POP = NA CC0603N AGND R244 4.7K MIC1R-VREFO
CC0603N
R246 4.7K MIC1L-VREFO
AGND 37 24
38 CBP LINE2-L(PORT-E-L) 23
+V5_PVDD C246 10uF LDO2-CAP 39 AVSS2 LINE2-R(PORT-E-R) 22 +V5_AVDD
AGND LDO2-CAP LINE1-L(PORT-C-L)
CC0603N
AVDD2 40
41 AVDD2
PVDD1
LINE1-R(PORT-C-R)
MIC1-R(PORT-B-R)
21
20 AUD_MIC1_IN_R C250 2.2uF CC0603N INNER_MIC
INNER_MIC 28
MIC Jack
C247 SPK_L+ 42 19 AUD_MIC1_IN_L C249 2.2uF CC0603N
100NF C248 +V5_PVDD SPK_L- 43 SPK-OUT-L+ MIC1-L(PORT-B-L) 18 AUD_MIC_IN_R POP = NA
CC0402N SPK_R- 44 SPK-OUT-L- MIC2-R(PORT-F-R) 17 AUD_MIC_IN_L R250 0 ohm
10uF SPK-OUT-R- MIC2-L(PORT-F-L) AGND
CC0805N SPK_R+ 45 16
46 SPK-OUT-R+ MONO-OUT 15 R252 20K RC0402N R253 R255 R254 0 ohm
AGND
GPIO0/DMIC-DATA
PD# 47 PVDD2 JDREF 14 100k 10k J1 PJ-342G
GPIO1/DMIC-CLK
MIC_SEL_SPDIF 48 PDB Sense B 13 R251 39.2K RC0402N EARPHONE_SEL RC0402N RC0402N 2
C251 SPDIF-OUT/GPIO2 Sense A HP_OUT_R 4
SDATA-OUT
100NF C252 R256 20K RC0402N MUTE_MIC EARPHONE_SEL A_EARPHONE_SEL 5
LDO3-CAP
SDA TA-IN
DVDD-IO
PCBEEP
RESETB
CC0402N 10uF A_MUTE_MIC 7
DVDD
6
SYNC
CC0805N Placement near Audio CodecPOP = NA HP_OUT_L
DVSS
BCLK
3
Q11
C E1 3 C
E1 2N7002LT1
+V3.3S_AUDIO AUD_MIC_IN R257 0 ohm POP = NA
S D
+V3.3S_AUDIO +V1.5S_AUDIO TH-EARPHONE-282P-6N
1
1
2
3
4
5
6
7
8
9
10
11
12
G R259 0 ohm
R601 1k POP = NA
2
FB10 180ohm FB0603N
C517 100NF POP = NA R600 10k POP = NA R258 R260
Audio Jack R261
10k
SPKR 10 RC0402N
0 0
HDA_RST# 8,24 AGND POP = NA
C254
10uF
C255
100NF
C253
10uF
RC0603N
POP = NA
RC0603N match to R298 R299
HDA_SYNC 8
CC0603N CC0402N CC0603N
AUDIO_DVDD_IO
AGND
+V3.3S_AUDIO DMIC_DATA R262 33 RC0402N C256
HDA_SDATAIN0 8
DMIC_CLK 100NF
CC0402N
HDA_BITCLK 8
C258 100NF CC0402N POP = NA C257 22pF CC0402N
3
Q12
AGND 2N7002LT1
S D
1
G
2
R268
+V3.3S 10k
RC0402N
AGND POP = NA
B R269 C262 B
AGND
10K 100NF
RC0402N CC0402N
U24
5
1
26 EC_MUTE#
4 PD#
2
+V3.3S PD#=0V : Power down Class D SPK amplifer
PD#=3.3V : Power up Class D SPK amplifer
3
R270
10K
+V3.3S RC0402N
R271
100k
3
RC0402N
Q13
D
2N7002LT1
1
G R272
S
2
0 CN11
3
SMD-CN-100P-4BN
1k
4ohm 2W/8ohm 1W can support
A A
Title <Title>
Size Sheet Rev
Audio Codec
D Name A
ENGINEER: golden Date: Tuesday, May 06, 2014 Sheet 24 of 38
8 7 6 5 4 3 2 1
5 4 3 2 1
+V3.3S
R637
10K
+V3.3S RC0402N
POP = NA
WIFI_3P3_RST#
D D
R590
100k
3
+V3.3S RC0402N
POP = NA Q67
D
2N7002LT1
1 POP = NA
G
S
2
3
C263 C264 C265
Minicard-WIFI
CC0603N 0.1u 0.1u Q68
S D
10uF CC0402N CC0402N BSS138
POP = NA 1 POP = NA
9 WIFI_PCIE_RST G
2
+V1.5S
CN12
+V3.3S R636 0 RC0402N 1 2
9 PCIE_WIFI_WAKE# 3 WAKE# +3.3V_1 4
BT_ON R278 0 RC0402N 5 RSVD1 GND7 6 C266 C267
7 RSVD2 +1.5V_1 8 CC0603N 0.1u +V3.3A
9 CLKREQ# UIM_PWR1 10 10uF CC0402N
GND1 UIM_DATA
1
5
2N7002LT1 KEY U58
R635 0 POP = NA 17 18 +V3.3S 1 WIFI_3P3_RST#
19 RSVD3 GND8 20 R279 0 RC0402N WIFI_PERST# 4
RSVD4 W_DISABLE# WIRELESS_ON 26
21 22 WIFI_PERST# 2
GND3 PERST# BUF_PLT_RST# 9,19,23,26
23 24
8 PCIE_RXN1_WLAN 25 PER_N0 +3.3V_AUX 26 SN74LVC1G08DCKR
8 PCIE_RXP1_WLAN PER_P0 GND9
3
27 28 Co-Lay sot65p190-5n
29 GND4 +1.5V_2 30 R280 0 RC0402N C268 POP = NA
GND5 SMB_CLK SMB_CLK_S2 10,14,23
C 31 32 R281 0 RC0402N SMB_DATA_S2 10,14,23 0.1u C
8 PCIE_TXN1_WLAN PET_N0 SMB_DATA
33 34 CC0402N R589 0 RC0402N
8 PCIE_TXP1_WLAN PET_P0 GND10
35 36
GND6 USB_D- HUB_USB_PN3 17
+V3.3S 37 38
RSVD5 USB_D+ HUB_USB_PP3 17
39 40
41 RSVD6 GND11 42
43 RSVD7 LED_WWAN# 44
C269 C270 45 RSVD8 LED_WLAN# 46
0.1u 0.1u 47 C_CLK LED_WPAN# 48
CC0402N CC0402N 49 C_DAT +1.5V_3 50
51 C_RST GND12 52
RSVD12 +3.3V_2
E1
E2
E3
SD-80053-001
E1
E2
E3
R282 0 RC0402N
26 BT_ON
B B
A A
Title <Title>
Size Sheet Rev
Minicard-Wifi
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 25 of 38
5 4 3 2 1
5 4 3 2 1
+V1.8A +V3.3A
Layout Note:
R290 0 RC0402N POP = NA VBAT
R776 10k LPC debug Port +V3.3A_KBC
+V3.3A_RTC R291 0 RC0402N
Recommended net "+V3.3A" and
"+V3.3A_RTC" minimum trace
C379 C380
(KBC Debug Port) width 12mils.
0.1u 0.1u +V3.3S
CC0402N CC0402N +V3.3A +V3.3A_KBC
VREG3
E1
CN14
U96 1 +V3.3A_KBC
E1
1 6 2 1 R670 0 RC0805N
2 VCCAVCCB 5 3 2 +V3.3A_KBC
LPC_SERIRQ 3 GND OE 4 LPC_SERIRQ_EC BUF_PLT_RST# 4 3 R764 0 RC0805N
10,26 LPC_SERIRQ A B 4
2
LPC_AD3 5 POP = NA
LPC_AD2 6 5 C281 D27
TXB0101DCKR 6
LPC_AD1 7 FB13 180 FB0603N +V3.3AVCC 10uF SOT95P280-3N
R648 0 LPC_AD0 8 7 CC0603N POP = NA 3
LPC_FRAME# 9 8
POP = NA LPC_CLK_EC 10 9 F2T20U-XXT3-E C282 C283
11 10 SMD-CN-50P-20N-H 10uF 0.1u
LPC_SERIRQ_EC 12 11 CC0603N CC0402N
12
1
+V3.3A 13 +V3.3A_KBC
D +V1.8A 14 13 D
15 14 +V3.3A_KBC
16 15 25 WIRELESS_ON
17 16 +V3.3A_KBC
17 31 DIS_BAT
1
R298 10k 18 Q69 I2C_CLK3 R294 10k RC0402N
19 18
G
POP = NA C285 20 19 28 CAPLOCK_LED RSMRST#_EC 3 2 I2C_DATA3 R295 10k RC0402N
E2
20 D S 2N7002LT1 PM_RSMRST# 9
2
C284
0.1u
0.1u
CC0402N
Note: 19,30 SMC_SHUTDOWN#
R301 0 RC0402N
POP = NA D28 I2C_CLK1 R296 10k RC0402N
For IT8928 PIN3=GPH7 28 NUMLOCK_LED
E2
CC0402N R332 0 RC0402N SOT95P280-3N
POP = NA R248 0 POP = NA R328 0 RC0402N POP = NA 3 I2C_DATA1 R297 10k RC0402N
8,26 FLASH_TXE AC_PRESENT 9
Co-Lay
12
1
U26
11 +V3.3A_KBC
R701
R702
0
0
POP = NA
SMC_ONOFF# 26,30 Co-Lay I2C_CLK0 R299 10k RC0402N
VCCA OE VCCB 5A_ONOFF 26,32
2 10 LPC_SERIRQ_EC I2C_DATA0 R300 10k RC0402N
10,26 LPC_SERIRQ A1 B1 3G_LED 28
1
3 9 H_RCIN# +V3.3A R322 0
9 PMC_RSTBTN 4 A2 B2 8 PMC_PWRBTN#_EC
MIC_SEL_DET 24 Allocation USB Devices I2C_CLK2 R302 10k RC0402N
GND
+V3.3A
+V3.3AVCC
POP = NA POP = NA
I2C_DATA3 31 SMBUS1 Battery LID R306 10k RC0402N
I2C_CLK3 31
P
Co-Lay R700 R304
SMBUS2 Thermal Sensor/PS8625
VBAT
GA20_EC 0 0 D7 +V3.3A_KBC
R327 RC0603N RC0603N sod2514n R307 0 RC0402N
100k POP = NA POP = NA
LPC_CLKRUN# 10 SMBUS3 Charger IC
3
R653 0 R756 10k POP = NA POP = NA
N
R654 0 R757 10k Q63 U28 +V5S
S D
R655 0 R758 10k 2N7002LT1 IT8528E/VG
1 POP = NA
G
114
121
127
107
TBCLK R310 10k RC0402N
11
26
50
92
74
84
83
82
56
57
33
19
20
99
98
97
96
95
94
93
10 LPC_AD[3..0]
2
+V3.3A
3
TBDATA R316 10k RC0402N
+V1.8A +V1.8A
3
LPC_AD0 10 110 I2C_CLK0
CTX1/SOUT1/GPH2/SMDAT3/ID2
VSTBY6
VSTBY5
VSTBY4
VSTBY3
VSTBY2
EGCLK/GPE3
EGCS#/GPE2
EGAD/GPE1
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5
GINT/CTS0#/GPD5
L80HLAT/BAO/GPE0
L80LLAT/GPE7
DTR1#/SBUSY/GPG1/ID7/FDIO2
HMOSI/GPH6/ID6
HMISO/GPH5/ID5
HSCK/GPH4/ID4
HSCE#/GPH3/ID3
CRX1/SIN1/SMCLK3/GPH1/ID1
CLKRUN#/GPH0/ID0
VCC
AVCC
VSTBY1(PLL)
VBAT
Q88 LPC_AD1 9 LAD0/GPM0 SMCLK0/GPB3 111 I2C_DATA0
S D
2N7002LT1 LPC_AD2 8 LAD1/GPM1 SMDAT0/GPB4 115 I2C_CLK1 R750 100 RC0402N
SM BUS
LAD2/GPM2 SMCLK1/GPC1 SMB_CLK_BT 31
1 POP = NA LPC_AD3 7 116 I2C_DATA1 R749 100 RC0402N
9 PMC_SUSPWRDNACK G LAD3/GPM3 SMDAT1/GPC2 SMB_DATA_BT 31
R313 10k R312 100 22 117 I2C_CLK2
9,19,23,25 BUF_PLT_RST# LPCRST#/GPD2 SMCLK2/PECI/GPF6
2
R314 13 118 I2C_DATA2
10 LPC_CLK_EC LPCCLK/GPM4 SMDAT2/PECIRQT#/GPF7
100k POP = NA C287 6 I2C_CLK2 R672 0 POP = NA
10 LPC_FRAME# LFRAME#/GPM5 I2C_CLK2_THEM
C286 0.1u 85
PS2CLK0/TMB0/GPF0/CEC TBCLK 28
0.1u CC0402N R317 0 POP = NA LPCPD# 17 86 I2C_DATA2 R673 0 POP = NA
LPCPD#/GPE6 PS2DAT0/TMB1/GPF1 TBDATA 28 I2C_DATA2_THEM
SOC_WAKE_SCI CC0402N 87
PS2CLK1/DTR0#/GPF2 ALL_SYS_PWRGD 19
POP = NA GA20_EC 126 88
PS/2
GA20/GPB5 PS2DAT1/RTS0#/GPF3 EC_DELAY_ALL_SYS_PWRGD 19
POP = NA LPC_SERIRQ_EC 5 89
12
5 A3 B3 7 LPCPD# PWUREQ#/GPC7/BBO
9 PMC_SUS_STAT# A4 B4
C RUNTIME_SCI#_EC R319 0 RC0402N 24 C
PWM0/GPA0 WP 31
TXB0104RUTR 25
PWM1/GPA1 BL_ADJ 21
6
IT8528E/VG
R656 0 POP = NA R762 10k POP = NA
CS_WAKE_EC 120
+V3.3A_KBC TMRI0/GPC4 V1P2A_VR_PWRGD 35
124 R329 0 POP = NA R330
TMRI1/GPC6 PM_SLP_S0IX# 9,19,22,33,37
10k
24 DMIC_LEFT_RIGHT
R326
20K ±1% R333 R703
Co-Lay
0 POP = NA
RC0402N
POP = NA +V3.3S
5A_ONOFF 26,32
POP = NA 100k 125 R704 0
RC0402N PWRSW/GPE4 18 PMC_PWRBTN#_EC SMC_ONOFF# 26,30
RI1#/GPD0 21
VSPI_KBC
WAKE UP RI2#/GPD1
R335 4.7k POP = NA
PM_BATLOW# 9
R311 5.6k POP = NA R660
CS_WAKE WRST# 35 10k
RTS1/GPE5 EC_BLEN 21
112 RC0402N
RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 WIFI_PWRON 28
Please do not place any pull-up POP = NA
C288 R658 CN25
1uF resistor on GPG0, GPG2, and GPG6 0 109 R661 100 POP = NA 2 E2
CC0402N (Reserved hardware strapping). POP = NA UARTTXD/SOUT0/GPB1 108 R710 0
CHG_LED 28
2 E2
RXD/SIN0/GPB0
1 E1
66 1 E1
ADC0/GPI0 IOUT 31
R712 0 106 67 R342 0 RC0402N R717 0 POP = NA SMD-CN-80P-2N
8,26 FLASH_TXE GPG0/FSCE1#/SSCE1# ADC1/GPI1 VBAT_EC 31 MIC_SEL_SPDIF 24
FSCK 105 68 POP = NA
FSCK ADC2/GPI2 DDR3L_EVENT 14
R331 0 POP = NA IT8928_VSS 104 69
DSR0#/GPG6/FIOO3 ADC3/GPI3 PM_SLP_S4# 9,33
FMISO 103 FLASH 70 For Home Button +V3.3A
SW1 FMISO ADC4/GPI4 PM_SLP_S3# 9,18,22,33,36
N
FMOSI 102 71
SW2 FMOSI ADC5/DCD1/GPI5 ADP_IN# 30
4 3 1 3 FSCE# 101 72 R341 1k RC0402N D30
4 3 FSCE# ADC6/DSR1/GPI6 BAT-DEK# 31
100 A/D D/AADC7/CTS1/GPI7 73 AOZ8231 BAT-DEK# R336 100k RC0402N
21 TP_EN SSCE0#/GPG2
6 5 2 4 SOD0806N ADP_IN# R338 10k RC0402N
6 5 X0 36 POP = NA PROCHOT#_EC R340 10k RC0402N POP = NA
KSO0/PD0
P
X1 37
2 1 X2 38 KSO1/PD1
2 1 SKRMABE010 KSO2/PD2
X3 39 76 PROCHOT#_EC
40 KSO3/PD3 TACH2/HDIO2/GPJ0 77
+V3.3A_KBC VSPI_KBC
TMG-533-S-T/R(180GF) X4
KSO4/PD4 KBMX HDIO3/GPJ1
R674 0 POP = NA
SOC_FLASHEN 9
SW_TMG-53N POP = NA X5 41 78
X6 42 KSO5/PD5 DAC2/GPJ2/TACH0B 79 CAM_ON 17
X7 43 KSO6/PD6 DAC3/GPJ3/TACH1B 80 WIFI_LED 28
D37 KSO7/PD7 DAC4/DCD0#/GPJ4 PWR_LED_RED 28
X8 44 81
P N 45 KSO8/ACK# DAC5/RIG0#/GPJ5 PWR_LED_GRN 28
Reset Button X9
X10 46 KSO9/BUSY
+V1.8A_SPI_KBC BAT54WS-7-F X11 51 KSO10/PE 2
52 KSO11/ERR# CK32KE/GPJ7 128
B R334 0 POP = NA X12
KSO12/SLCT CLOCK
CK32K/GPJ6
B
KSI3/SLIN#
KSI1/AFD#
53
KSI0/STB#
X13
KSI2/INIT#
54 KSO13
Co-Lay X14
VCORE
55 KSO14
AVSS
X15 R343 C289 10pF CC0402N
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
KSI4
KSI5
KSI6
KSI7
R339 0 POP = NA KSO15 0
X[15..0] RC0402N
27 X[15..0]
POP = NA R344
58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
1
X6 10M +V3.3S
VSPI_KBC
1
X5 RC0402N
Close to PIN-VCC 3 2 Q13MC1461000200SM26BSPRC
POP = NA
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
POP = NA
2
C290
4
VSPI_KBC 0.1u C292
Y[0..7] CC0402N U29 100nF
27 Y[0..7]
C293 C291 10pF CC0402N 1 5 CC0402N
0.1u R345 R659 NC VCC POP = NA
CC0402N 4.7K 0 Layout Note: PROCHOT#_EC 2
R346 RC0402N A
32.768kHz clock lines: 3 4
4.7K
RC0402N FSCE# 1
U30 EN25F16-100HIP
8
For IT8928 a. If possible, please avoid using any R347 GND Y H_PROCHOT# 8
FMISO 2 CS# VCC 7 PIN 113=NA R292 through-hole. 100K SN74LVC1G06DCK
SO/SIO1 HOLD#
3
WP#/ACC SCLK
6 FSCK PIN 122=NA 0 b. Please make the trace length short, and RC0402N POP = NA C294
4 5 FMOSI POP = NA 47pF
GND SI/SIO0 the trace width wide enough. CC0402N
SOIC127P800-8N c. The spacing to the closest neighbor POP = NA
should be wide enough.
+V3.3A_KBC
Co-Lay
10UH
C569 0.1u CC0603N L16 1 2 LC4340N POP = NA
POP = NA
4.7uH
Just For IT8928 C570 R689 1
U76
6 L17 1 2 LC5757N POP = NA
C571
10uF
C572
10uF
+V3.3A_KBC +V1.8A_SPI_KBC 22pF 100k BS LX CC0603N CC0603N
CC0402N 2 5
GND IN POP = NA
POP = NA POP = NA
U70 3 4 R686 10k RC0402N
1 5 FB EN
2 IN OUT SY8200ABC POP = NA
R657 0 POP = NA 3 GND 4 POP = NA C568
C507 SHDN NC C521 R688 R687 4.7UF
1uF APL5320-18BI 1uF 22.1k ±1% 1M CC0603N R708 0 RC0603N POP = NA +V_DC
CC0402N POP = NA CC0402N POP = NA POP = NA
POP = NA POP = NA
POP = NA
Vout=0.6*(1+Ru/Rd)
A
APL5101-18AI P2P APL5320-18BI A
Title <Title>
Size Sheet Rev
KBC_IT8528E
D Name A
ENGINEER: golden Date: Sunday, May 04, 2014 Sheet 26 of 38
5 4 3 2 1
5 4 3 2 1
HDD CONN
CN28 S1
C295 0.01uF CC0402N S2 S1
8 SATA_TXP1 S2
C296 0.01uF CC0402N S3
8 SATA_TXN1 S3
S4
C297 0.01uF CC0402N S5 S4
8 SATA_RXN1 S5
C298 0.01uF CC0402N S6
8 SATA_RXP1 S6
S7
S7
P1 SAF-21M1BX-XX-5X-020
D P2 P1 TH-SATA-127P-22n-R-KX D
P3 P2
P4 P3
Imax=1A
P5
P6
P4
P5 Keyboard Connector
R747 1 P7 P6 Y[0..7]
+V5S P7 26 Y[0..7]
P8 SMD-FPC-100P-26BN-H +V3.3A
P9 P8
Y0 26
P9 26
Imax=1A P10
P10
Y1 25
P11 Y2 24 25 Y0 R348 10k RC0402N
P12 P11 24
Y3 23 Y1 R349 10k RC0402N
P13 P12 23
Y4 22 Y2 R350 10k RC0402N
P14 P13 X[15..0] 22
C299 Y5 21 Y3 R351 10k RC0402N
C300 P15 P14 26 X[15..0] 21
10uF Y6 20 Y4 R352 10k RC0402N
0.1u P15 20
CC0805N Y7 19 Y5 R353 10k RC0402N
CC0402N X15 18 19 Y6 R354 10k RC0402N
X14 17 18 Y7 R355 10k RC0402N
X13 16 17
X12 15 16
X11 14 15
X10 13 14
X9 12 13
X8 11 12
X7 10 11
X6 9 10
X5 8 9 E2
X4 7 8 E2 E1
X3 6 7 E1
X2 5 6
X1 4 5
X0 3 4
2 3
ODD CONN
GND
1 2
1
CN15
CN29 S1
SATA_TXP0 C274 0.01uF CC0402N S2 S1
+V5S +V3.3S 下接触
C
8 SATA_TXP0 SATA_TXN0 C273 0.01uF CC0402N S3 S2 For ODD C
8 SATA_TXN0 S4 S3
SATA_RXN0 C272 0.01uF CC0402N S5 S4 R283 R284
8 SATA_RXN0 S5
8 SATA_RXP0 SATA_RXP0 C271 0.01uF CC0402N S6 0 0 Co-Lay
S7 S6 RC0603N RC0603N FB12
S7 +V5S_ODD
R748 0 RC0402N P1
POP = NA
P1 POP = NA
P2 U25
+V5S_ODD P3 P2 5 180ohm
P4 P3 VIN
FB0603N 1
P5 P4 R285 0 POP = NA 4 VOUT
P6 P5 C275 SS C278
Imax=1.3A 5V P6 4.7UF C276 C277 3 2 0.1u
CC0603N 1uF 0.01uF EN/ENBGND CC0402N
SAF-21S0CX-XX-50-025 POP = NA CC0603N CC0402N APL3512A/B
C773 C774 C775 TH-SATA-100X127P-13N POP = NA POP = NA SOT95P280-5N
10uF 0.1u 0.1u
CC1206N CC0402N CC0402N POP = NA
POP = NA R286
新料 10k
POP = NA
USE APL3512A High Enable
Tss=0.2*Css*Vin
26 MSATA_POWER_ON
C1.0T-1-10AWB
DUAL LAY POP = NA R287
10 10k
SATA_RXP0 C781 0.01uF CC0402N POP = NA 9 10 RC0402N
SATA_RXN0 C780 0.01uF CC0402N POP = NA 8 9 POP = NA
7 8
SATA_TXN0 C782 0.01uF CC0402N POP = NA6 7 E2
SATA_TXP0 C783 POP = NA 5 6
0.01uF CC0402N E2 E1
4 5 E1
3 4
2 3
1 2
1
B B
5V
CN33
A A
Title <Title>
Size Sheet Rev
SATA Ports & KB CONN
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 27 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
+V1.8S
+V3.3S_SD
+V3.3S +VSDIO
J 2
S D
3 R789 J
167mA
TO USB BOARD
0
C799 Q60 U97
10uF APM2301CAa8 1 8
VIN1 VOUT1
G
CC0603N R782 sot95p280-3n +V3.3S 2 7
+V3.3S 100k C804 3 VIN2 VOUT2 6
ON CT
1
+V5S RC0402N +V3.3S 2.2uF 4 5
E1
+V1.8S PWR_SD_GATE_EN R785 CC0603N VBIAS GND
POP = NA C784 R781 R786 100k TPS22965 C803 C800 C801
E1
3
10uF 10k 10k RC0402N +V5A 1000pF 0.01uF 2.2uF
+V3.3S_SD 10V RC0402N Q105 RC0402N CC0402N CC0402N CC0603N
S D
±20% 24 R779 2N7002LT1 C798 V1P8S_SDIO_EN
24
3
23
CC0603N 10k 1 C802
C785 22 23 RC0402N G 0.01UF Q110 100NF
S D
22
2
I I
3
10uF 21 POP = NA Q104 SOT95P240-3N 2N7002LT1 CC0402N
CC0603N 20 21 BSS138 1
S D
20 G
3
POP = NA 19 SOT95P280-3N Q109
19
2
18 28 SD3_PWREN 1 BSS138 SOT95P240-3N
S D
17 18 G SOT95P280-3N
17 HUB_USB_PN2 17 ANPEC APL3526 P2P TI TPS22965
2
16 28 SD3_1P8EN 1
17 HUB_USB_PP2 16 G
3
15 Q108
17 USB_OC2#_HUB 15
2
14 R780 BSS138
S D
R753 0 POP = NA 13 14 10k SOT95P280-3N
17 HUB_USB_PN4 13
R754 0 POP = NA 12 RC0402N 28 SD3_PWREN 1
17 HUB_USB_PP4 12 G
8 SD_CLK R751 0 11 POP = NA
11
2
R752 0 10 +V3.3A
8 SD_CMD 8 SD_D0 10
8 SD_D1 9 E2
8 9 E2 E1
8 SD_D2 8 E1
7 U98
8 SD_D3 7
H H
8 SD_CD 6 +V3.3S 1 8
5 6 2 VIN1 VOUT1 7
8 SD3_WP 5 VIN2 VOUT2
4 C809 3 6
24 INNER_MIC 4 ON CT
3 R783 2.2uF 4 5
E1
AGND 3 VBIAS GND
2 100k CC0603N
1 2 RC0402N TPS22965 C808
30 POWSW# 1
E1
+V5A 1000pF
CN18 V3P3S_SDIO_EN CC0402N
3
Q106
S D
SOT95P280-3N 100NF
28 SD3_1P8EN 1 CC0402N
+V3.3S G
+V3.3A
2
C304
G C303
0.1u
0.1u G
3
CC0402N Q107
CC0402N
POP = NA BSS138
POP = NA
S D
SOT95P280-3N
CN21 1
28 SD3_PWREN G
1
1
2
2
2 3
3 4
4 5
E1 5 6
E1 6 7 L_BUTTON
E2 7 8 R_BUTTON
E2 8 9
9 10
F 10
11
12
11
12
PWR_LED_GRN
PWR_LED_RED
26
26
F
13
13 CHG_LED 26
14
14 WIFI_LED 26
15
15 3G_LED 26
16
16 CAPLOCK_LED 26
17
17 NUMLOCK_LED 26
18
18 19 LID
19 20 LID 26
20 +V3.3S
+V1.8S
R359
E 10k
RC0402N E
1
Q18
CN17
G
3 2 1
D S BSS138 SATA_LED# 8 1 2 R778 0
2 USB_PN2 10
E1 3 R777 0
E1 3 USB_PP2 10
E2 4
E2 4 5
5 6
6 TP_VCC
SMD-CN-100P-6L
+V5S
A Title <Title>
A
Size Sheet Rev
LEDS & Buttons
C Name A
ENGINEER: golden Date: Tuesday, May 06, 2014 Sheet 28 of 38
10 9 8 7 6 5 4 3 2 1
J J
P
POP = NA POP = NA
SOD0806N SOD0806N
AOZ8231 AOZ8231
D12 D13
N
R360 0 RC0603N
+V5A
10 USB_PN0
4FIL_175P200X120-4L
3
B3
USB3.0 Port1
Co-Lay
GND
FIL5 330mA POP = NA
F3 1 2 f1206n 1 2
10 USB_PP0 UNB
J2
B2
VCC1_USB3.0 1
C309 R361 0 RC0603N VBUS
VCC1_USB3.0 10uF 2 E1
D_MINUS GND2
I CC0603N
POP = NA
5
U31
1 VCC1_USB3.0
R362 0 RC0603N 3
4
D_PLUS GND3
GND4
E2
E3
E4
I
R363 VIN VOUT 1 UNB B22 GND1 GND5
10 USB3_RX0_N
1.8k ±1% 3 5
RC0603N OCB C310 C311 C312 FIL6 330mA POP = NA 6 StdA_SSRX-
POP = NA 4 2 10uF 10uF 1000pF GND
4 B33 StdA_SSRX+
EN GND 10 USB3_RX0_P
CC1206N CC1206N CC0402N FIL_175P200X120-4L 7
TPS2065 POP = NA GND_DRAIN
10 USB_OC0#
SOT95P280-5N R364 0 RC0603N 8
POP = NA 9 StdA_SSTX-
C313 R365 StdA_SSTX+
0.1u 1k ±1% +V5A R366 1k RC0402N POP = NA R367 0 RC0603N BMXX09X-XX-XX
CC0402N RC0603N TH-USB-200X150P-9FN
POP = NA POP = NA C314 100nF CC0402N 1 UNB B22
10 USB3_TX0_N
H APL3511C P2P TPS2065
C315 100nF CC0402N
FIL7
GND
4 B33
330mA POP = NA H
10 USB3_TX0_P
FIL_175P200X120-4L
26,29 USB3_PWRON
R368 0 RC0603N
1
U32 U33
D+
D+
D-
D-
TPD2EUSB30DRTR TPD2EUSB30DRTR
GND
GND
POP = NA POP = NA
3
G G
+V5S
Co-Lay
F5 1 2 f1206n
C611
USB2.0 Port2
F F
P
VCC2_USB3.0 10uF POP = NA POP = NA
CC0603N SOD0806N SOD0806N
POP = NA U81 AOZ8231 AOZ8231 J4
5 1 VCC2_USB3.0 D34 D33
R738 VIN VOUT R742 0 RC0603N VCC2_USB3.0 1
VBUS
N
1.8k ±1% 3 3
RC0603N OCB C606 C609 C607 4FIL_175P200X120-4L
3 D_PLUS E1
17 HUB_USB_PN1 GND2
4 2 E2
B3
POP = NA 10uF 10uF 1000pF
GND
EN GND CC1206N CC1206N CC0402N FIL9 330mA POP = NA GND3 E3
TPS2065 POP = NA 1 2 2 GND4
17 USB_OC1#_HUB 17 HUB_USB_PP1 D_MINUS
4 E4
UNB
SOT95P280-5N
B2
POP = NA GND1 GND5
C608 R739 R741 0 RC0603N
0.1u 1k ±1% +V5S R740 1k RC0402N POP = NA
CC0402N RC0603N
E POP = NA POP = NA
APL3511C P2P TPS2065
BYND04XXXXX
TH-USB-200X250P-4LN E
26,29 USB3_PWRON
D D
C MARK3 MARK4
MH1
贴铜柱
C
MH6 MH5
MH7
MH3
A Title <Title>
A
Size Sheet Rev
USB Ports
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 29 of 38
10 9 8 7 6 5 4 3 2 1
ADP_IN
J J
FB17
FB0603N 120ohm +V_ADP_IN
1
CN22
2 AC_IN MAX 5A FB18
3
120ohm
4 FB0603N
N
I PJ-023D C768 C769 C770
I
5
P
The same as M330
GND
H H
Power Sequence
G 05 G
Power Button Detect & Latch +V_DC
+V_DC_IN
Co-Lay
Q19 AO4419
1 8
2 7
3 6
5
C494 C495 C316 SOIC127P600-8N C460 C461 C319
4
4.7UF 4.7UF 0.1uF C320 R369 4.7UF 4.7UF 0.1uF
F CC0603N CC0603N
POP = NA
CC0603N 0.1uF
CC0603N
390K
RC0603N
CC0603N CC0603N
POP = NA
CC0603N
F
PWRONLATCHG R370
100
RC1206N
R371
100k
RC0402N
Power Sequence
3
E Q20
E
S D
R372 7AC 4BAT PS_LATCH# 1
G
2N7002LT1
SOT95P240-3N
1M R373
2
RC0402N 1M
RC0402N
D14 sod2514n
N P
ADP_IN# 26
D 31 ACOK#
N
D15
P sod2514n D
D16
POWSW# N P sod2514n R374 0 RC0402N
28 POWSW#
D17
N P sod2514n
SMC_ONOFF# 26
3
Q21
S D
2N7002LT1
1 SOT95P240-3N
19,26 SMC_SHUTDOWN# G
2
C R375
C
100k
RC0402N
B B
A Title <Title>
A
Size Sheet Rev
DC_IN & Power Good
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 30 of 38
10 9 8 7 6 5 4 3 2 1
J J
C333
0.1uF
CC0603N
+VBAT_DET
+VBAT
CN23
+V3.3A F4 1 2 f6125n 1
+V3.3A_KBC R320 POP = NA 2 1
WP 3 2 E1
26 WP 3 E1
10k RC0402N 4 E2
26 BAT-DEK# 4 E2
R787 0 RC0402N 5
5
I R788 0 RC0402N
26
26
SMB_CLK_BT
SMB_DATA_BT
6
7
8
6
7
I
POP = NA 9 8
9
duallay C334
22pF
C335
22pF
CC0402N CC0402N
+V_DC
+V_DC_IN
D18 R391
BAT54C 0
H H
SOT95P240-3N RC0603N
2 1
+V_ADP
+V_ADP_IN
3
F6 Q26 Q27 AC current limit: 3.64A Co-Lay
2 1 8 AO4468 1 1 AO4468 8 R392 0.01 RC2512N
C336 7 2 C337 2 7 C338 C339
R393 2200pF 6 3 0.1uF 3 6 10UF 10uF C340
2.2 3216FF-2A 5 5 R394 CC1206N CC1210N
CC0603N 0.1uF
RC0805N C341 C342 f1206n CC0603N 0 PHASE POP = NAPOP = NA CC0603N
4
4
10UF 10uF C343 RC0402N D19
CC1206N CC1210N 0.1uF C344 0.1uF CC0603N C346
C345 POP = NA CC0603N N P +VBAT
1
2
2.2uF POP = NA Q28 BSS138 Q29
G CC0805N Dual Lay 3
D S
2SOT95P280-3N
VCC_CHG 0.047uF
CC0603N APM4910K D 5
6 L5 1
sod5225n AO4419
Q30 8
G
R396 R395 R767 0 HDRV 8 7 1 2 R397 0.01 RC2512N 2 7
G
N
N
1
3M 10 SOIC127P600-8N D21 4.7uH 3 6
RC0603N SK34L CP27
+ C347C348 5
1
RC0402N POP = NA D20 LDRV3 sod5225n 10UF C350 C351 SOIC127P600-8N C496
R399
4
R398 POP = NA R401 C349 sod2514n S POP = NA 100uF 4.7UF 4.7UF
10 0.1uF
2
4.02k 1uF POP = NA POP = NA 4.7UF CC0603N
R4004.02k C352 1uF CC0603N CC0603N
P
4
P
CC0603N CC1206N POP = NA
RC0603N 1M RC0603N AGND_CHG CHGREGN AGND_CHG
R768 CC0603N R402
POP = NA 0
AGND_CHG 10k
20
19
18
17
16
U41 POP = NA
C353 C354 E1 RC0603N BATDRV R403 4.02K
PHASE
HIDRV
BTST
VCC
REGN
0.1uF 0.1uF E1 C355 0.1uF CC0603N
F CC0603N CC0603N
C357 C358 RC0603N R404
C356 F
1 BQ24715 15 AGND_CHG 0.1uF 0.1uF 10k 0.01uF
2 ACN LODRV 14 CC0603NCC0603N CC0402N
ACP GND R406 10 RC0603N POP = NA
CMSRC 3 13 POP = NA
VCC_CHG ACDRV 4 CMSRC SRP 12 R405 7 RC0603N
ACOK 5 ACDRV SRN 11 BATDRV
ACOK BATDRV
CHGREGN R407 10K R409
ACDET
12K 内部地做短接 +VBAT_DET
CELL
IOUT
RC0402N
SDA
SCL
R410 RC0603N
750K
RC0603N
Layout NOTE:
6
7
8
9
10
R412
AGND_CHG 110K±1%
E ACDET The AGND_CHG connect to RC0402N
E
AGND_CHG
C359 100pF CC0402N GND through E1 pin;
R414
26 IOUT
R416 0 RC0402N POP = NA
by via only! CHGREGN +V3.3A
VBAT_EC 26
120K R415
RC0603N 30k ±1%
R408 POP = NA RC0402N
26 I2C_DATA3 10k
RC0402N R411
26 I2C_CLK3 10k
AGND_CHG
RC0402N
GND
D CELL_SELECT
D
ACOK# 30
3
3
Q32
S D
Q33 2N7002LT1
S D
2N7002LT1 1
G DIS_BAT 26
ACOK R420 1k RC0402N 1
19 ACOK G
2
2
C AGND_CHG
R418
100k
C
AGND_CHG R419 0 RC0603N POP = NA
Via E1 Pin
AGND_CHG
AGND_CHG
B B
A Title <Title>
A
Size Sheet Rev
Power Charger & Battery Conn
C Name A
ENGINEER: golden Date: Sunday, May 04, 2014 Sheet 31 of 38
5 4 3 2 1
+V_DC +V_DC
VREG3
C368
D D
C546 C360 C361 C363 1uF C366 C367 C364 C547
4.7UF 4.7UF 4.7UF 0.1uF 4.7UF 4.7UF 0.1uF 4.7UF
CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N
POP = NA R421 POP = NA
±1% 20K
RC0603N
R422
VREG3
R423 30k ±1% VFB1 20K ±1%
RC0603N RC0603N
1
2
3
4
5
TPS51275/C
CS1
VFB1
VREG3
VFB2
CS2
+V3.3A
+V5A +V5A/5.5A R428
VREG3 R427 10k EN1 20 6 EN2 10k VREG3 100k R390 +V3.3A
OCP=7A EN1 EN2
2
1
1
2
VCLK 19 7 +V3.3A/5A
D VCLK PGOOD 3A5A_PWRGD 34,35 D
5 18 8 5
2.2uH 6 C369 0.1u 17 SW1 SW2 9 C370 0.1u 6 2.2uH
OCP=7A
L6 1 2 LC6666N 7 8 DRVH1 R429 2.2 RC0603N 16 VBST1 VBST2 10 R430 2.2 RC0603N DRVH2 8 7 L7 1 2 LC6666N
LL1 DRVH1 DRVH2 LL2
VREG5
DRVL1
DRVL2
N
Q35 E1 Q34
E1
VO1
D23 APM4910K 3 DRVL1 R432 0 RC0603N DRVL2 3
VIN
R431 0 RC0603N APM4910K
N
1
1
C776 C777 CP4 CP5 SOIC127P600-8N
SK34L S S SOIC127P600-8N CP7 C374 C373
1
C371 C372 10uF 10uF + + sod5225n D35 CP6 C779
+ C778 2.2uF 0.1u
15
14
13
12
11
4
0.1u 2.2uF 10V 10V POP = NA SK34L + 10uF 10uF CC0603N CC0402N
P
CC0402N CC0603N ±20% ±20% 150uF 220UF sod5225n 150uF CC0603N CC0603N
2
2
CC0603N CC0603N CCP7343NCAE630W570HN POP = NA 220UF CCP7343N
2
POP = NA CAE630W570HN
POP = NA
VREG5 VREG5
Co-Lay
Co-Lay C375
C 1uF C
+V_DC
C376
0.1uF
CC0603N
Q43
G
Q98 Q42 2N7002LT1 H=Disable 1.0A and 1.8A
1
G
G
APM2301CAa8 APM2301CAa8 POP = NA L=Enable 1.0A and 1.8A
sot95p280-3n sot95p280-3n
1
POP = NA POP = NA
1P0A_ONOFF 26
5A_ONOFF 26
R665 0 POP = NA
VR_ALW_EN 18,19
R486 0 POP = NA
B B
A A
Title <Title>
Size Sheet Rev
+V5A & +V3.3A
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 32 of 38
5 4 3 2 1
5 4 3 2 1
+V5S
R384
10k
RC0402N
POP = NA
D D
+V_DC
Co-Lay
R433 0 POP = NA DDR_STBY R434 0 RC0402N POP = NA
9,19,22,26,37 PM_SLP_S0IX#
3
Q36
BSS138
S D
SOT95P280-3N C383 C542 C543 C544 C545
Set Fsw=400kHZ on D-CAP Mode 1 = NA
POP 0.1uF 4.7UF 4.7UF 4.7UF 4.7UF
G S3_DISCHARGE 18,34,35,37
For tps51716 , It must pop 1K CC0603N CC0603N CC0603N CC0603N CC0603N
2
R436 200K ±1% RC0402N R438
110K±1%
RC0402N
+VSM
20
19
18
17
16
U43 R441 0 RC0603N
1
2
+1.5V/8.5A
MODE
TRIP
S3
S5
PGOOD
+VSM_VTT C385 0.1u CC0402N D 5 +VSM
1 15 R442 0 RC0603N C386 0.1uF CC0603N 6 OCP=9A
+V0.75M 2 VTTSNS VBST 14 8 7 1.0uH
Iout MAX=2A 3 VLDOIN
VTT
DRVH
SW
13 L8 1 2 LC6666N
4 12
VDDQSNS
+V5A Q37
C387 5 VTTGND V5IN 11 R443 0 RC0603N 3 APM4910K
VTTREF DRVL
REFIN
PGND
10uF S SOIC127P600-8N
VREF
GND
1
CC0603N C388
E1
4
1uF + CP9 C791 C792 C391
TPS51216 CC0603N 330uF 10uF 10uF 0.1u
6
7
8
9
10
E1
CCP7343N CC0603N CC0603N CC0402N
2
POP = NA POP = NA
R446 和R447改为一颗30K的即可得1.35V
+V3.3A
+VSM
B B
R449
10k
C767 R448 RC0402N R450 0 POP = NA VCORE_VRON 36
100NF 100k
RC0402N
DDR3_DRAM_PWROK 6
S4_DISCHARGE
3
S D
+VSM
R576
470
RC0402N
SLP_S4# DISCHARGE CIRCUIT POP = NA
DESIGNED FOR ~100ms
3
2N7002LT1
RAILS. 1 POP = NA
G
2
A A
Title <Title>
Size Sheet Rev
Power_DDR3/DDR3L
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 33 of 38
5 4 3 2 1
5 4 3 2 1
+V_DC
D D
C404
0.1u
R733 0 CC0402N
9,35 V1P8A_VR_PWRGD
C444 C443 C407 C405 C459
4.7UF 4.7UF 4.7UF 0.1uF 4.7UF
R457 0 POP = NA CC0603N CC0603N CC0603N CC0603N CC0603N
32,35 3A5A_PWRGD
POP = NA POP = NA
N
R459 For SOC and V1.0S=0.202A+5.487A=6A
3
2.2 D26
Q49 +V5A RC0603N BAT54WS-7-F
S D
2N7002LT1 R460 SOD1713N
1 +V3.3A 220K±1%
18,35 ALW_DISCHARGE G
P
RC0402N +V1.0A
14
2
1
2
U47
R461 D 5 +V1.0A/6A
EN_PSV
VBST
R462 300 ±1% 6 1.5uH
100k RC0603N 2 13 R463 0 RC0603N 8 7 L9 1 2 LC6666N OCP=8A
RC0402N 3 TON DRVH 12
4 VOUT LL 11 R464 10k ±1% RC0603N Q40
5 V5FILT
TPS51117RGYTRIP 10 3 APM4910K
VFB V5DRV +V5A
1
R466 0 RC0402N POP = NA 6 9 R467 0 RC0603N S SOIC127P600-8N
35 V1P0A_VR_PWRGD PGOOD DRVL
+ CP11 C412
4
PGND
330uF 0.1uF
GND
C413 C411 CCP7343N CC0603N
E1
2
For APW7141 Must be 2.2ohm 1uF 1uF
CC0402N CC0402N Rtrip=Vtrip/10
E1
Iocp=Vtrip/Rdson+Iripple/2
R468
10k ±1%
RC0603N
C Vout=0.75*(1+R1/R2) C
R470
30k ±1%
RC0603N
+V1.05S P=(1.35-1.05)*1.5=0.45W
+V1.05S/1.5A
+VSM
R477
100K
R503 RC0402N
100K
RC0402N +V3.3A R474 100K RC0402N POP = NA
+V3.3A
V1P05S_VR_PWRGD 37
V1P05S_EN R476 0 RC0402N
R500
100k
3
+V1.0S RC0402N
3
Q73
S D
2N7002LT1 Q74
S D
1 SOT95P240-3N 2N7002LT1
G 1 SOT95P240-3N
18,33,35,37 S3_DISCHARGE G
2
R377
2
10k
RC0402N
3
D
1 G Q72
WNM2020-3
sot95p240-3Bn
2
S
A A
Title <Title>
Size Sheet Rev
+V1.0A & +V1.05S
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 34 of 38
5 4 3 2 1
5 4 3 2 1
+V1.8S
+V3.3A +V1.8A
P=(3.3-1.8)*0.43=0.645W
+V1.8A
+V1.8A/300mA
U51
D D
1 8 C422 100NF
+V5A 2 VIN1 VOUT1 7 C551 10uF CC0603N POP = NA
C425 C437 C529 C426 3 VIN2 VOUT2 6
C538 C423 C424 10uF 10uF 10uF 0.1u C550 4 ON CT 5
E1
10uF 10uF 0.1u C565 1uF CC0603N CC0603N CC0603N CC0402N 10uF VBIAS GND
CC0603N CC0603N CC0402N POP = NA C564 R480 CC0603N C427 TPS22965 C428
E1
POP = NA U50 22pF 15k ±1% POP = NA 1uF +V5A 1000pF
10 1 CC0402N RC0603N CC0402N CC0402N
9 VCNTL VOUT1 2
8 VIN3 VOUT2 3 C429
7 VIN2 VOUT3 4 1P8A_FB 100NF
6 VIN1 FB 5 CC0402N
E1 ENB POK
E1 Vout=0.8*(1+Ru/Rd)
34 V1P0A_VR_PWRGD
APL5932C/D +V3.3A ANPEC APL3526 P2P TI TPS22965
TDFN50P300X300-10N R482
R732 0 12k ±1%
32,34 3A5A_PWRGD
V1P5S_VR_PWRGD
R483
C766 100K
3
100NF RC0402N
3
Q50
S D
2N7002LT1 Q82
S D
1 V1P8A_VR_PWRGD 2N7002LT1
18,34 ALW_DISCHARGE G V1P8A_VR_PWRGD 9,34
1 SOT95P240-3N
18,33,34,35,37 S3_DISCHARGE G
2
2
V1P8A_VR_PWRGD R715 0 POP = NA
V1P2A_VR_PWRGD 26
C C
+V1.5S
+V5A
+V1.5S/58mA+
+V1.8A
+V3.3A
2N7002LT1
1 SOT95P240-3N +V3.3A R488 100K RC0402N
G POP = NA
2
RC0402N
Q70
1 WNM4002-3/TR
Note: Need APL5932A/B
B
SOT50P160-3BN High Enable B
3
2
Q86
POP = NA
S D
2N7002LT1
1
G S3_DISCHARGE 18,33,34,35,37
2
R247 0 RC0402N
A A
Title <Title>
Size Sheet Rev
+V1.8A & +V1.2A & +V1.5S
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 35 of 38
5 4 3 2 1
5 4 3 2 1
VCORE_CIMON
R505
270K ±1%
RC0402N
VCORE_OCP_I C448
0.22uF
+VCORE_VREF R506
75K ±1%
RC0402N
D R507
10.7K ±1% C449
D
RC0603N 100pF +V_DC
CC0402N
Co-Lay
11 VCORE_GSNS +V3.3A
R509 100 ±1%
33 VCORE_VRON
R511 34K ±1% RC0402N VCORE_CSP1
R497 0 VR_ON
9,18,22,26,33 PM_SLP_S3#
1
+V5A R512
+V3.3A + CP25 C456 C457 C458 100K_NTC
C596 100uF 1uF 4.7UF 4.7UF RC0402N
VCORE_COMP
VCORE_THERM
1uF CAE660W800HN CC0603N CC0603N CC0603N
VCORE_CIMON
VCORE_OCP_I
2
VCORE_CSN1
VCORE_CSP1
CC0402N R514 POP = NA C462 C463 C464
POP = NA 先用1500-0000-0393 75ohm替代 R513 +VCORE_VREF
10
RC0402N
R515
30K ±1%
3900pF
CC0402N
270pF
CC0402N
0.022uF
POP = NA
0 R519
RC0402N 28.7K ±1%
+V1.0S RC0402N
C467 VCORE_CSN1
12
11
10
9
8
7
6
5
4
3
2
1
C465 C466 2.2uF
1uF 0.33UF CC0603N
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
CTHERM
CGFB
CVFB
CCOMP
CIMON
COCP-I
2
CC0402N CC0603N
D1 L14 +VCORE
R516 R517 R518 CF_IMAX 13 48 V5_CORE R520 0 RC0603N 1 0.36uH
CF-IMAX V5 G1
73.2 ±1% 73.2 ±1% 73.2 ±1% 14 47 LC7266N
15 VREF CDH1 46 R521 2.2 RC0603N C468 0.1u CC0603N 1 2
VR_ON 16 V3R3 CBST1 45
VCORE_PWRGD 17 VR_ON CSW1 44 R526 0 RC0603N 6 Q41
CPGOOD CDL1 G2
R522 20±1% 18 U56 43 V5_CORE C469 4.7UF CC0603N SM7302ESKP R524
9 SVID_CLK VCLK V5DRV
1
R523 0 19 TPS59641TSL 42 KPAK127P605-9N 2.2
9 SVID_ALERT# ALERT# QFN40P600X600-48AN PGNG
R525 16.9 ±1% 20 41 S2 S1/D2 RC0603N C796 C795 + CP12 + CP13 C470 C471 C472
9 SVID_DATA VDIO CDL2
VR_HOT# 21 40 POP = NA 22uF 22uF 330uF 330uF 22uF 22uF 22uF
SLEWA 22 VR_HOT# CSW2 39 CC0805N CC0805N CCP7343N CCP7343N CC0805N CC0805N CC0805N
3
4
5
7
SLEWA CBST2
2
GFX_PWRGD 23 38
GPGOOD CDH2 POP = NA
C C
GF_IMAX 24 37 R527 10k RC0402N C473
GSKIP#_1
GF-IMAX VBAT +V_DC
GTHERM
+V1.0S 1000pF
GCOMP
CPWM3
CSKIP#
GOCP-I
GIMON
GPWM
GCSN
GGFB
GCSP
CC0402N
GVFB
POP = NA
E1
Co-Lay
25
26
27
28
29
30
31
32
33
34
35
36
E1
R528
33
VCORE_GIMON
VCORE_SKIP#
VGFX_THERM
R529 0 RC0402N
VGFX_COMP
VGFX_OCP_I
VGFX_SKIP#
VGFX_CSN
VR_HOT#
VGFX_CSP
GFX_PWM
8 VR_HOT#
VGFX_GSNS
+V3.3A
11 VGFX_VSNS
R531 VCORE_GIMON
100k
RC0402N +VCORE_VREF C474 100pF CC0402N
R534
GFX_PWRGD R533 11K ±1% RC0603N 210K ±1% +V_DC
37 GFX_PWRGD
RC0402N
+V3.3A VGFX_OCP_I
Co-Lay
C475
0.22uF
C485 C486 C487 C488
R538 4.7UF 4.7UF 4.7UF 4.7UF
R537 75K ±1% CC0603N CC0603N CC0603N CC0603N
100K RC0402N
RC0402N
VCORE_PWRGD
37 VCORE_PWRGD
1
C491 C492 C493 + CP26 R532 33K ±1% RC0402N VGFX_CSP
1uF 4.7UF 4.7UF 100uF
CC0603N CC0603N CC0603N CAE660W800HN
2
POP = NA R535
100K_NTC
RC0402N
B R539
28.7K ±1%
RC0402N
RC0402N CC0402N CC0402N POP = NA
B
+VCORE_VREF
VGFX_CSN
R540 2.2 RC0603N C480 0.1u CC0603N
+VGFX
2
L15
U57 D1 0.36uH
1 8 R667 0 RC0603N 1 LC7266N
BST DRVH G1
GFX_PWM 2 7 1 2
R542 R543 R544 R545 R546 R547 R548 VGFX_SKIP# 3 PWM SW 6
665k ±1% 169K±1% 665k ±1% 15.8k ±1% 15.8k 0 0 C479 1uF CC0603N V5_CORE 4 SKIP# GND 5
E1
RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N VDD DRVL R666 0 RC0603N 6 Q87 R541
G2
1
POP = NA POP = NA TPS51604 SM7302ESKP 2.2
E1
VCORE_SKIP# KPAK127P605-9N RC0603N + CP14 C481 C482 C483 C793 + CP18 C794
S2 S1/D2 POP = NA 330uF 22uF 22uF 22uF 22uF 330uF 22uF
VGFX_SKIP# CCP7343N CC0805N CC0805N CC0805N CC0805N CCP7343N CC0805N
2
3
4
5
7
POP = NA
VGFX_THERM C484
1000pF
VCORE_THERM CC0402N
GF_IMAX
POP = NA Co-Lay
SLEWA
CF_IMAX
A A
Title <Title>
Size Sheet Rev
POWER VCORE & GFXCORE
D Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 36 of 38
5 4 3 2 1
5 4 3 2 1
+VSM
+V1.0A +V1.0S
U45
1 8 C396 100NF
U46 2 VIN1 VOUT1 7 C557 10uF CC0603N POP = NA
1 8 C403 100NF 3 VIN2 VOUT2 6
2 VIN1 VOUT1 7 C446 10uF CC0603N 4 ON CT 5
E1
3 VIN2 VOUT2 6 C556 VBIAS GND
4 ON CT 5 10uF C399 TPS22965 C400 +V1.35S +VSFR
E1
VBIAS GND
E1
D D
C445 C408 CC0603N 1uF +V5A 1000pF
10uF 1uF TPS22965 C409 POP = NA CC0402N CC0402N
E1
CC0603N CC0402N +V5A 1000pF R676 0 RC0603N
CC0402N C402
100NF R452 0 RC0603N
C410 CC0402N
100NF
CC0402N ANPEC APL3526 P2P TI TPS22965
ANPEC APL3526 P2P TI TPS22965
R472 0 RC0402N
V1P05S_VR_PWRGD 34
V1P0S_EN R493 0
VCORE_PWRGD 36
R458 0
GFX_PWRGD 36
3
3
Q75
S D
Q81 2N7002LT1
S D
2N7002LT1 1 SOT95P240-3N
18,33,34,35,37 S3_DISCHARGE G
1 SOT95P240-3N
18,33,34,35,37 S3_DISCHARGE G
2
2
+V1.0S +V1.0SX
R678 0 RC0603N
R677 0 RC0603N
C C
+V3.3S
+V3.3A
U68
1 8
+V5A +V5S 2 VIN1 VOUT1 7
3 VIN2 VOUT2 6
4 ON CT 5
E1
U69 VBIAS GND
1 8 C497 TPS22965 C447 C498 C499
VIN1 VOUT1
E1
2 7 10uF +V5A 1000pF 0.01uF 10uF
3 VIN2 VOUT2 6 CC0603N CC0402N CC0402N CC0603N
4 ON CT 5 +V1.8S
E1
3
3
Q84
S D
Q54 BSS138
S D
2N7002LT1 1
G S3_DISCHARGE 18,33,34,35,37
1
G S3_DISCHARGE 18,33,34,35,37
2
2
A A
Title <Title>
Size Sheet Rev
Power_S3_S4
C Name A
ENGINEER: golden Date: Wednesday, March 05, 2014 Sheet 37 of 38
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
Changelist
J Changelist v1.01 J
1、增加FLASH_TXE和5A_ONOFF信号----------兼容ITE8928预留
2、DDR电源更改layout
3、增加CP5,CP6并duallay
4、增加信号LPC_SERIRQ电平转换电路
5、cn32,cn30管脚会短路,拉开间距-------layout更改
6、CN29光驱定义反,需更改
I 7、增加SD3_WP信号,删除cardread的USB信号
I
Changelist v1.02
1、变更信号LPC_SERIRQ电平转换电路
2、USB配置重新调整,CAMERA 触摸屏,SD
3、SD卡SDIO电源配置预留
H H
G G
F F
E E
D D
C C
B B
A A
Xiamen Exprot Processing Zone,
Haicang District,Xiamen,China,361026
Title <Title>
Size Sheet Rev
Change List
D Name A
ENGINEER: golden Sunday, May 04, 2014 38 of 38
Date: Sheet
10 9 8 7 6 5 4 3 2 1