32 CHAPTER TWO 9Ch in THX will result in a delay of exactly .0002 seconds before the overflow flag is set if a 6 megahertz crystal is used. Timer Mode 3 Timers 0 and 1 may be programmed to be in mode 0, 1, or 2 independently of a similar mode for the other timer. This is not true for mode 3; the timers do not operate indepen- dently if mode 3 is chosen for timer 0. Placing timer | in mode 3 causes it to stop count. ing; the control bit TRI and the timer | flag TFI are then used by timer 0. Timer 0 in mode 3 becomes two completely separate 8-bit counters. TLO is controlled by the gate arrangement of Figure 2.11 and sets timer flag TFO whenever it overflows from FFh to 00h. THO receives the timer clock (the oscillator divided by 12) under the control of TRI only and sets the TF1 flag when it overflows, Timer 1 may still be used in modes 0, 1, and 2, white timer 0 is in mode 3 with one important exception: No interrupts will be generated by timer 1 while timer 0 is using the TF overflow flag. Switching timer 1 to mode 3 will stop it (and hold whatever count is in timer 1). Timer 1 can be used for baud rate generation for the serial port, or any other mode 0, 1, or 2 function that does not depend upon an interrupt (or any other use of the FI flag) for proper operation. Counting The only difference between counting and timing is the source of the clock pulses to the counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide-by-124 circuit. When used as a counter, pin TO (P3.4) supplies pulses to counter 0, and pin TI (P3.5) to counter 1. The C/T bit in TMOD must be set to 1 to enable pulses from the TX pin to reach the control circuit shown in Figure 2.11 ‘The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change ‘on the input from high to low between samples will increment the counter. Each high and low state of the input pulse must thus be held constant for at least one machine cycle to ensure reliable counting. Since this takes 24 pulses, the maximum input frequency that can be accurately counted is the oscillator frequency divided by 24. For our 6 megahertz, crystal. the calculation yields a maximum external frequency of 250 kilohertz Serial Data Input/Output ‘Computers must be able to communicate with other computers in modern multiprocessor distributed systems. One cost-effective way to communicate is to send and receive data bits serially. The 8051 has a serial data communication circuit that uses register SBUF to hold data. Register SCON controls data communication, register PCON controls data rates, and pins RXD (P3.0) and TXD (P3.1) connect to the serial data network. SBUF is physically two registers. One is write only and is used to hold data to be transmitted our of the 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h, There are four programmable modes for serial data communication that are chosen by setting the SMX bits in SCON. Baud rates are determined by the mode chosen. Figure 2.13 shows the bit assignments for SCON and PCON. Serial Data Interrupts Serial data communication is a relatively slow process, occupying many milliseconds per data byte to accomplish. In order not to tie up valuable processor time, serial data flags areFIGURE 2.13 SCON and PCON Function Registers 7 6 5 4 3 2 1 0 alee ‘THE SERIAL PORT CONTROL (SCON) SPECIAL FUNCTION REGISTER Bit Symbol Function 7 smo Serial port mode bit 0. Set/cleared by program to select mode. 6 MI Serial port mode bit 1. Set/cleared by program to select mode SMO SM1_—- Mode Description 0 0 o Shift register: baud = £/12 0 1 1 Bit UART; baud = variable 1 0 2 S-bit UART! baud = 1/32 or {164 1 1 3 it UART; baud = variable 5 sM2 Multiprocessor communications bit. Set/cleared by program to enable multiprocessor ‘communications in modes 2 and 3. When set to 1 an interrupt is generated if bit 9 of the received data is a 1; no interrupt is generated if bit 9is a0. If set to 1 for mode 1, 1 intertupt will be generated unless a valid stop bit is received. Clear to 0 if mode 0 isin use 4 REN Receive enable bit. Set to 1 to enable reception; cleared to 0 to cissable reception. 3 188 Transmitted bit 8. Set/ceared by program in modes 2 and 3. 2 R88 Received bit 8. Bit 8 of received data in modes 2 and 3, stop bit in mode 1. Not used in mode 0 1 oon Transmit interrupt fiag, Set to one atthe end of bit 7 time in mode 0, and atthe beginning Of the stop bit for other modes. Must be cleared by the program. oR Receive interrupt flag. Set to one at the end of bit 7 time in mode 0, and halfway through the stop bit for other modes. Must be cleared by the program, Bit addressable as SCON.0 to SCON.7 Pee eee HB iecre@cte EHS @eee ee ieee: oo eee ‘THE POWER MODE CONTROL (PCON) SPECIAL FUNCTION REGISTER Bit symbol Function 7 SMOD —_ Serial baud rate modify bit. Set to 1 by program to double baud rate using timer 1 for modes 1, 2, and 3. Cleared to 0 by program to use timer 1 baud rate. 64 Not implemented. 3 GFT General purpose user flag bit 1. Set/cleared by program. 2 FO General purpose user flag bit 0. Set/cleared by program. + Power down bit, Set to 1 by program to enter power down configuration for CHMOS processors. om {dle mode bit. Set to 1 by program to enter idle mode configuration for CHMOS processors. PCON is not bit addressable.34 cHarTeR TWO included in SCON to aid in efficient data transmission and reception. Notice that data transmission is under the complete control of the program, but reception of data is unpre- dictable and at random times that are beyond the control of the program. ‘The serial data flags in SCON, TI and RI. are set whenever a data byte is transmitted (Tor received (RI), These flags are ORed together to produce an interrupt to the pro- -gram. The program must read these flags to determine which caused the interrupt and then clear the flag. This is unlike the timer flags that are cleared automatically; it is the respon- sibility of the programmer to write routines that handle the serial data flags. Data Transmission Transmission of serial data bits begins anytime data is written to SBUF. TI is set to a when the data has been transmitted and signifies that SBUF is empty (for transmission purposes) and that another data byte can be sent. If the program fails to wait for the TI flag, and overwrites SBUF while a previous data byte is in the process of being transmitted, the results will be unpredictable (a polite term for “garbage out”). Data Reception Reception of serial data will begin ifthe receive enable bit (REN) in SCON is set to 1 for all modes. In addition, for mode 0 only, RI must be cleared to 0 also. Receiver interrupt flag RI is set after data has been received in all modes. Setting REN is the only direct program control that limits the reception of unexpected data; the requirement that RI also be 0 for mode 0 prevents the reception of new data until the program has dealt with the old data and reset RI Reception can begin in modes 1, 2, and 3 if RI is set when the serial stream of bits begins. RT must have been reset by the program before the last bit is received or the incoming data will be lost. Incoming data is not transferred to SBUF until the last data bit hhas been received so that the previous transmission can be read from SBUF while new data is being received. Serial Data Transmission Modes ‘The 8051 designers have included four modes of serial data transmission that enable data communication to be done in a variety of ways and a multitude of baud rates, Modes are selected by the programmer by setting the mode bits SMO and SMI in SCON. Baud rates, are fixed for mode 0 and variable, using timer | and the serial baud rate modify bit (SMOD) in PCON, for modes 1, 2, and 3. Serial Data Mode 0—Shift Register Mode Setting bits SMO and SMI in SCON to 00b configures SBUF to receive of transmit eight data bits using pin RXD for both functions. Pin TXD is connected to the internal shift frequency pulse source to supply shift pulses to external circuits. The shift frequency, or baud rate, is fixed at 1/12 of the oscillator frequency, the same rate used by the timers when in the timer configuration. The TXD shift clock is a square wave that is low for machine cycle states $3~S4~S5 and high for S6~S1—S2. Figure 2.14 shows the timing for mode 0 shift register data transmission. ‘When transmitting, data is shifted out of RXD; the data changes on the falling edge of S6P2, or one clock pulse after the rising edge of the output TXD shift clock. The sys- tem designer must design the external circuitry that receives this transmitted data to re- ceive the data reliably based on this timing.THE BOSI ARCHITECTURE «35 FIGURE 2.14 Shift Register Mode 0 Timing XD Data Out THO Clock appa ie [09 TY 01 Shit Data ut ‘sore bo tt ot br tba Tos toe 1 os 1 be 1 oy 1 extemal pata Bits Smittez out 1t2i3t4;s5tetvz7ztat er i ie Ti 1 I 1 Ay} i} At I p 2 13 it i ie 7 Ie ‘S3P1_| S6PI | | 1 1 1 1 | External Data Bits Shifted Ia i 1 1 i 1 , 1 ui 4 ser shift Daten Received data comes in on pin RXD and should be synchronized with the shift clock produced at TXD. Data is sampled on the falling edge of SSP2 and shifted in to SBUF on the rising edge of the shift clock. Mode 0 is intended not for data communication between computers, but as 2 high- speed serial data-collection method using discrete logic to achieve high data rates. The baud rate used in mode 0 will be much higher than standard for any reasonable oscillator frequency; for a 6 megahertz crystal, the shift rate will be 500 kilohertz. Serial Data Mode 1—Standard UART When SMO and SMI are set to 01b, SBUF becomes a 10-bit full-duplex receiver/ transmitter that may receive and transmit data at the same time. Pin RXD receives all data, and pin TXD transmits all data. Figure 2.15 shows the format of a data word. ‘Transmitted data is sent as a start bit, eight data bits (Least Significant Bit, LSB, first), and a stop bit. Interrupt flag TI is set once all ten bits have been sent, Each bit interval is the inverse of the baud rate frequency, and each bit is maintained high or tow cover that interval Received data is obtained in the same order; reception is triggered by the falling edge of the start bit and continues if the stop bit is true (0 Jevel) halfway through the start bit interval. This is an anti-noise measure; if the reception circuit is triggered by noise on the transmission line, the check for a low after half a bit interval should limit false data reception. Data bits are shifted into the receiver at the programmed baud rate, and the data word will be loaded to SBUF ¢f the following conditions are true: RI must be 0, and mode bit SM2 is 0 or the stop bit is 1 (the normal state of stop bits). RI set to 0 implies that the program has read the previous data byte and is ready to receive the next; a normal stop bit will then complete the transfer of data to SBUF regardless of the state of SM2. SM2 set to O enables the reception of a byte with any stop bit state, a condition which is of limited use in this mode, but very useful in modes 2 and 3. SM2 set to 1 forces reception of only “good” stop -noise safeguard Of the original ten bits, the start bit is discarded, the eight data bits go to SBUF, and the stop bit is saved in bit RB8 of SCON. RI is set to 1, indicating a new data byte has been received.36 © CHAPTER TWO FIGURE 2.15 Standard UART Data Word | LEP E TE 1 foe a eee eH eee eee eee ee ee ‘Start Bit pasaaaanS Data Bits Minimum of One Stop Bit 1 BitTime = — 1 ._— If RI is found to be set at the end of the reception, indicating that the previously received data byte has not been read by the program, or if the other conditions listed are not true, the new data will not be loaded and will be lost. Mode 1 Baud Rates ‘Timer 1 is used to generate the baud rate for mode 1 by using the overflow flag ofthe timer to determine the baud frequency. Typically, timer 1 is used in timer mode 2 as an autoload 8-bit timer that generates the baud frequency: fw 2m —_oteillator Frequency ‘owt 32d” 12d x [256d — (THI) SMOD is the control bit in PCON and can be 0 or 1, which raises the 2 in the equation to a value of | or 2. If timer 1 is not run in timer mode 2, then the baud rate is 3Moo feet = fa = Gage * (timer 1 overflow frequency) and timer I can be run using the internal clock or as @ counter that receives clock pulses from any external source via pin TL ‘The oscillator frequency is chosen to help generate both standard and nonstandard bauid rates. If standard baud rates are desired. then an 1.0592 megahertz crystal could be selected. To get a standard rate of 9600 hertz then, the setting of THI may be found as follows: 2° 11.0592 x 10" = 2564 - (22. s =} THI = 256d (S 7 ) 253.0000d = OFDh if SMOD is cleared to 0. Serial Data Mode 2—Multiprocessor Mode Mode 2 is similar to mode | except 11 bits are transmitted: a start bit, nine data bits, and a stop bit, as shown in Figure 2.16. The ninth data bit is gotten from bit TBS in SCON during transmit and stored in bit RB8 of SCON when data is received. Both the start and stop bits are discarded, ‘The baud rate is programmed as follows: soo fio = “Giq7 ¥ oscillator frequencyTHE 8051 ARCHITECTURE «37 FIGURE 2.16 Multiprocessor Data Word Ile State 2 el ae a feet See eee eee lr petoy fe fe] oF Efe a Minimum of bata ats One Stop Bit sitine = — Interrupts Here, as in the case for mode 0, the baud rate is much higher than standard communica- tion rates. This high data rate is needed in many multi-processor applications. Data can be collected quickly from an extensive network of communicating microcontrollers if high baud rates are employed. ‘The conditions for setting RI for mode 2 are similar to mode 1: RI must be 0 before the last bit is received, and SM2 must be 0 or the ninth data bit must be a 1. Setting RI based upon the state of SM2 in the receiving 8051 and the state of bit 9 in the transmitted message makes multiprocessing possible by enabling some receivers to be interrupted by certain messages, while other receivers ignore those messages. Only those 8051's that have SM2 set to 0 will be interrupted by received data which has the ninth data bit set to 0; those with SM2 set to 1 will not be interrupted by messages with data bit 9 at 0. All re- ceivers will be interrupted by data words that have the ninth data bit set to 1; the state of M2 will not block reception of such messages. ‘This scheme allows the transmitting computer to “talk” to selected receiving comput- ers without interrupting other receiving computers. Receiving computers can be com- manded by the “talker” to “listen” or “deafen” by transmitting coded byte(s) with the ninth data bit set to 1. The 1 in data bit 9 interrupts all receivers, instructing those that are programmed to respond to the coded byte(s) to program the state of SM2 in their respec- tive SCON registers. Selected listeners then respond to the bit 9 set to 0 messages, while all other receivers ignore these messages. The talker can change the mix of listeners by transmitting bit 9 set to 1 messages that instruct new listeners to set SM2 to 0, while others are instructed to set SM2 to 1. Serial Data Mode 3 Mode 3 is identical to mode 2 except that the baud rate is determined exactly as in mode 1, using Timer 1 to generate communication frequencies. ‘A computer program has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump on the states of flags and port pins. The second responds to hardware signals. called interrupts, that force the program to call a sub-routine. Software techniques use up processor time that could be devoted to other tasks; interrupts take processor time only when action by the program is needed. Most applications of microcontrollers involve responding to events quickly enough to control the environment that generates the events (generically termed “real-